CY7C026A-15AXI Cypress Semiconductor Corp, CY7C026A-15AXI Datasheet - Page 11

CY7C026A-15AXI

CY7C026A-15AXI

Manufacturer Part Number
CY7C026A-15AXI
Description
CY7C026A-15AXI
Manufacturer
Cypress Semiconductor Corp
Datasheet

Specifications of CY7C026A-15AXI

Format - Memory
RAM
Memory Type
SRAM - Dual Port, Asynchronous
Memory Size
256K (16K x 16)
Speed
15ns
Interface
Parallel
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CY7C026A-15AXI
Manufacturer:
Cypress Semiconductor Corp
Quantity:
135
Part Number:
CY7C026A-15AXI
Manufacturer:
Cypress Semiconductor Corp
Quantity:
10 000
Switching Waveforms
Document #: 38-06046 Rev. *F
Notes
CE
23. R/W must be HIGH during all address transitions.
24. A write occurs during the overlap (t
25. t
26. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of t
27. To access RAM, CE = V
28. To access upper byte, CE = V
29. Transition is measured 500 mV from steady state with a 5 pF load (including scope and jig). This parameter is sampled and not 100% tested.
30. During this period, the I/O pins are in the output state, and input signals must not be applied.
31. If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the high impedance state.
DATA OUT
ADDRESS
ADDRESS
CE
DATA IN
DATA IN
to be placed on the bus for the required t
as short as the specified t
To access lower byte, CE = V
[27,28]
HA
[27,28]
is measured from the earlier of CE or R/W or (SEM or R/W) going HIGH at the end of write cycle.
R/W
R/W
OE
IL
PWE
, SEM = V
IL
.
IL
t
t
, LB = V
, UB = V
SA
SA
NOTE 30
Figure 6. Write Cycle No. 1: R/W Controlled Timing
Figure 7. Write Cycle No. 2: CE Controlled Timing
(continued)
SCE
IH
.
IL
or t
IL
SD
, SEM = V
, SEM = V
PWE
. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be
) of a LOW CE or SEM and a LOW UB or LB.
t
HZWE
IH
IH
.
.
[29]
t
t
AW
AW
t
t
WC
WC
t
t
SCE
PWE
[26]
t
t
SD
SD
PWE
or (t
HZWE
t
t
HA
HA
[23, 24, 25, 31]
[23, 24, 25, 26]
t
t
+ t
HD
HD
t
SD
LZWE
) to allow the I/O drivers to turn off and data
t
HZOE
NOTE 30
[29]
CY7C026A
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