CY7C025AV-25AC Cypress Semiconductor Corp, CY7C025AV-25AC Datasheet - Page 12

• Manufacturer Part Number: CY7C025AV-25AC
• Description: IC,SRAM,8KX16,CMOS,QFP,100PIN,PLASTIC
• Manufacturer: Cypress Semiconductor Corp

Document #: 38-06052 Rev. *H
Switching Waveforms
Write Cycle No. 2: CE Controlled Timing
Write Cycle No. 1: R/W Controlled Timing
Notes:
33. R/W must be HIGH during all address transitions.
34. A write occurs during the overlap (t
35. t
36. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of t
37. To access RAM, CE = V
38. To access upper byte, CE = V
39. Transition is measured ±500 mV from steady state with a 5-pF load (including scope and jig). This parameter is sampled and not 100% tested.
40. During this period, the I/O pins are in the output state, and input signals must not be applied.
41. If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the high-impedance state.
CE
DATA OUT
ADDRESS
ADDRESS
CE
DATA IN
DATA IN
[37, 38]
to be placed on the bus for the required t
as short as the specified t
To access lower byte, CE = V
HA
[37, 38]
R/W
R/W
is measured from the earlier of CE or R/W or (SEM or R/W) going HIGH at the end of write cycle.
OE
IL
PWE
, SEM = V
IL
.
IL
t
t
(continued)
SA
SA
, LB = V
, UB = V
NOTE 40
SCE
IH
.
IL
or t
IL
SD
, SEM = V
, SEM = V
PWE
. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be
) of a LOW CE or SEM and a LOW UB or LB.
t
[33, 34, 35, 41]
HZWE
[33, 34, 35, 36]
IH
IH
.
.
[39]
t
t
AW
AW
t
t
WC
WC
t
t
SCE
PWE
[36]
t
t
SD
SD
PWE
CY7C0241AV/0251AV/036AV
or (t
CY7C024AV/025AV/026AV
HZWE
t
t
HA
HA
t
t
HD
HD
+ t
t
SD
LZWE
) to allow the I/O drivers to turn off and data
t
HZOE
[39]
NOTE 40
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