CY7C025AV-25AC Cypress Semiconductor Corp, CY7C025AV-25AC Datasheet

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CY7C025AV-25AC

Manufacturer Part Number
CY7C025AV-25AC
Description
IC,SRAM,8KX16,CMOS,QFP,100PIN,PLASTIC
Manufacturer
Cypress Semiconductor Corp
Datasheets

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Part Number:
CY7C025AV-25AC
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Part Number:
CY7C025AV-25AC
Quantity:
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Part Number:
CY7C025AV-25AC
Manufacturer:
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Quantity:
20 000
1
Features
Notes:
Cypress Semiconductor Corporation
1.
2.
3.
4.
5.
• True dual-ported memory cells which allow simulta-
• 4/8/16K x 16 organization (CY7C024AV/025AV/026AV)
• 4/8K x 18 organization (CY7C0241AV/0251AV)
• 16K x 18 organization (CY7C036AV)
• 0.35-micron CMOS for optimum speed/power
• High-speed access: 15
• Low operating power
• Fully asynchronous operation
Logic Block Diagram
R/W
UB
OE
I/O
I/O
A
A
CE
OE
R/W
SEM
BUSY
INT
UB
LB
CE
LB
neous access of the same memory location
— Active: I
— Standby: I
0L
0L
Call for availability.
I/O
I/O
A
BUSY is an output in master mode and an input in slave mode.
L
8/9L
0L
L
L
L
0
L
L
L
L
–A
–A
L
–A
L
L
8
0
L
–I/O
–I/O
–I/O
L
11
[4]
11/1213L
[4]
11/12/13L
–I/O
[5]
for 4K devices; A
15
7
[3]
7/8L
for x16 devices; I/O
for x16 devices; I/O
[2]
15/17L
CC
SB3
= 115 mA (typical)
= 10 A (typical)
12/13/14
0
For the most recent information, visit the Cypress web site at www.cypress.com
8/9
8/9
–A
12
0
[1]
9
–I/O
–I/O
for 8K devices; A
/20/25 ns
8
Address
17
Decode
12/13/14
for x18 devices.
3.3V 4K/8K/16K x 16/18 Dual-Port Static RAM
for x18 devices.
0
–A
13
for 16K devices.
3901 North First Street
PRELIMINARY
Control
I/O
True Dual-Ported
Semaphore
RAM Array
Arbitration
Interrupt
M/S
• Automatic power-down
• Expandable data bus to 32/36 bits or more using Master/
• On-chip arbitration logic
• Semaphores included to permit software handshaking
• INT flag for port-to-port communication
• Separate upper-byte and lower-byte control
• Pin select for Master or Slave
• Commercial and industrial temperature ranges
• Available in 100-pin TQFP
• Pin-compatible and functionally equivalent to
Slave chip select when using more than one device
between ports
IDT70V24, 70V25, and 7V0261.
Control
I/O
CY7C0241AV/0251AV/036AV
San Jose
CY7C024AV/025AV/026AV
Address
Decode
12/13/14
CA 95134
12/13/14
8/9
8/9
November 29, 1999
I/O
A
A
8/9L
0R
0R
I/O
408-943-2600
–A
–A
[5]
–I/O
0L
[4]
11/12/13R
[4]
11/12/13R
–I/O
BUSY
SEM
R/W
15/17R
R/W
[2]
CE
INT
UB
LB
OE
OE
CE
UB
LB
[3]
7/8R
R
R
R
R
R
R
R
R
R
R
R
R
R

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CY7C025AV-25AC Summary of contents

Page 1

... BUSY is an output in master mode and an input in slave mode. For the most recent information, visit the Cypress web site at www.cypress.com Cypress Semiconductor Corporation PRELIMINARY 3.3V 4K/8K/16K x 16/18 Dual-Port Static RAM • Automatic power-down • Expandable data bus to 32/36 bits or more using Master/ Slave chip select when using more than one device • ...

Page 2

... Control of a semaphore indicates that a shared re- source is in use. An automatic power-down feature is con- trolled independently on each port by a Chip Select (CE) pin. The CY7C024AV/025AV/026AV and CY7C0241AV/0251AV/ 036AV are available in 100-pin Thin Quad Plastic Flatpacks (TQFP). 100-Pin TQFP Top View CY7C024AV (4K x 16) CY7C025AV ( CY7C024AV/025AV/026AV CY7C0241AV/0251AV/036AV ...

Page 3

Pin Configurations (continued) 100 I I/O 4 17L I/O 11L 5 I/O 6 12L I/O 13L 7 I/O 14L 8 GND 9 I/O 10 15L I/O 11 16L ...

Page 4

Pin Configurations (continued I I/O 4 17L I/O 11L 5 I/O 6 12L I/O 13L 7 I/O 14L 8 GND 9 I/O 10 15L I/O 11 16L GND I/O 14 ...

Page 5

Pin Definitions Left Port Right Port R/W R –A A –A 0L 13L 0R 13R I/O –I/O I/O –I/O 0L 17L 0R 17R SEM SEM ...

Page 6

Electrical Characteristics Over the Operating Range Parameter Description V Output HIGH Voltage ( Output LOW Voltage OL V Input HIGH Voltage IH V Input LOW Voltage IL I Output Leakage Current OZ I Input Leakage Current IX ...

Page 7

Switching Characteristics Over the Operating Range Parameter Description READ CYCLE t Read Cycle Time RC t Address to Data Valid AA t Output Hold From Address Change OHA [15 LOW to Data Valid ACE t OE LOW to ...

Page 8

Switching Characteristics Over the Operating Range Parameter Description [20] BUSY TIMING t BUSY LOW from Address Match BLA t BUSY HIGH from Address Mismatch BHA t BUSY LOW from CE LOW BLC t BUSY HIGH from CE HIGH BHC t ...

Page 9

Switching Waveforms Read Cycle No.1 (Either Port Address Access) ADDRESS OHA DATA OUT PREVIOUS DATA VALID Read Cycle No.2 (Either Port CE/OE Access) CE and DATA OUT I CC CURRENT I SB [23, ...

Page 10

Switching Waveforms (continued) Write Cycle No.1: R/W Controlled Timing ADDRESS OE [32,33 R/W NOTE 35 DATA OUT DATA IN Write Cycle No Controlled Timing ADDRESS [32,33 R/W DATA IN Notes: 28. R/W ...

Page 11

Switching Waveforms (continued) Semaphore Read After Write Timing, Either Side A –A VALID ADRESS SEM I R/W OE Timing Diagram of Semaphore Contention A – R/W L SEM L A –A ...

Page 12

Switching Waveforms (continued) Timing Diagram of Read with BUSY (M/S=HIGH) ADDRESS R R/W R DATA ADDRESS L BUSY L DATA OUTL Write Timing with Busy Input (M/S=LOW) R/W BUSY Note: 41 LOW. ...

Page 13

Switching Waveforms (continued) Busy Timing Diagram No.1 (CE Arbitration) CE Valid First: L ADDRESS L BUSY R CE Valid First: R ADDRESS L BUSY L Busy Timing Diagram No.2 (Address Arbitration) Left ...

Page 14

Switching Waveforms (continued) Interrupt Timing Diagrams Left Side Sets INT R : ADDRESS WRITE 1FFF (OR 1/3FFF R/W L INT R [44] t INS Right Side Clears INT R : ADDRESS R ...

Page 15

... CY7C026AV/36AV) is the mailbox for the right port and the second-highest memory location (FFE for the CY7C024AV/ 41AV, 1FFE for the CY7C025AV/51AV, 3FFE for the CY7C026AV/36AV) is the mailbox for the left port. When one port writes to the other port’s mailbox, an interrupt is generated to the owner ...

Page 16

Table 1. Non-Contending Read/Write Inputs CE R ...

Page 17

... Ordering Code [1] 15 CY7C024AV-15AC 20 CY7C024AV-20AC 25 CY7C024AV-25AC 8K x16 3.3V Asynchronous Dual-Port SRAM Speed (ns) Ordering Code [1] 15 CY7C025AV-15AC 20 CY7C025AV-20AC 25 CY7C025AV-25AC 16K x18 3.3V Asynchronous Dual-Port SRAM Speed (ns) Ordering Code [1] 15 CY7C026AV-15AC 20 CY7C026AV-20AC 25 CY7C026AV-25AC CY7C026AV-25AI 4K x18 3.3V Asynchronous Dual-Port SRAM Speed (ns) Ordering Code [1] 15 ...

Page 18

... Thin Plastic Quad Flat Pack (TQFP) A100 © Cypress Semiconductor Corporation, 1999. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user ...

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