CY14B256LA-SP45XI Cypress Semiconductor Corp, CY14B256LA-SP45XI Datasheet - Page 5

• Manufacturer Part Number: CY14B256LA-SP45XI
• Description: CY14B256LA-SP45XI
• Manufacturer: Cypress Semiconductor Corp
• Type: NVSRAMr

Specifications of CY14B256LA-SP45XI

• Format - Memory: RAM
• Memory Type: NVSRAM (Non-Volatile SRAM)
• Memory Size: 256K (32K x 8)
• Speed: 45ns
• Interface: Parallel
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Word Size: 8b
• Organization: 32Kx8
• Density: 256Kb
• Interface Type: Parallel
• Access Time (max): 45ns
• Package Type: SSOP
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 2.7V
• Operating Temp Range: -40C to 85C
• Pin Count: 48
• Mounting: Surface Mount
• Supply Current: 52mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Device Operation
The CY14B256LA nvSRAM is made up of two functional
components paired in the same physical cell. They are an SRAM
memory cell and a nonvolatile QuantumTrap cell. The SRAM
memory cell operates as a standard fast static RAM. Data in the
SRAM is transferred to the nonvolatile cell (the STORE
operation), or from the nonvolatile cell to the SRAM (the RECALL
operation). Using this unique architecture, all cells are stored and
recalled in parallel. During the STORE and RECALL operations,
SRAM
CY14B256LA supports infinite reads and writes similar to a
typical SRAM. In addition, it provides infinite RECALL operations
from the nonvolatile cells and up to 1 million STORE operations.
Refer to the
complete description of read and write modes.
SRAM Read
The CY14B256LA performs a read cycle when CE and OE are
LOW and WE and HSB are HIGH. The address specified on pins
A
accessed. When the read is initiated by an address transition,
the outputs are valid after a delay of t
is initiated by CE or OE, the outputs are valid at t
whichever is later (read cycle 2). The data output repeatedly
responds to address changes within the t
the need for transitions on any control input pins. This remains
valid until another address change or until CE or OE is brought
HIGH, or WE or HSB is brought LOW.
SRAM Write
A write cycle is performed when CE and WE are LOW and HSB
is HIGH. The address inputs must be stable before entering the
write cycle and must remain stable until CE or WE goes HIGH at
the end of the cycle. The data on the common I/O pins DQ
written into the memory if the data is valid t
a WE-controlled write or before the end of a CE-controlled write.
Keep OE HIGH during the entire write cycle to avoid data bus
contention on common I/O lines. If OE is left LOW, internal
circuitry turns off the output buffers t
AutoStore Operation
The CY14B256LA stores data to the nvSRAM using one of the
following three storage operations: Hardware STORE activated
by HSB; Software STORE activated by an address sequence;
AutoStore on device power-down. The AutoStore operation is a
unique feature of QuantumTrap technology and is enabled by
default on the CY14B256LA.
During a normal operation, the device draws current from V
charge a capacitor connected to the V
charge is used by the chip to perform a single STORE operation.
If the voltage on the V
automatically disconnects the V
operation is initiated with power provided by the V
Note If the capacitor is not connected to V
must be disabled using the soft sequence specified in
AutoStore
capacitor on V
operation without sufficient charge to complete the Store. This
will corrupt the data stored in nvSRAM.
Document Number: 001-54707 Rev. *F
0-14
determines which of the 32,768 data bytes each are
read
on page 7. In case AutoStore is enabled without a
Truth Table For SRAM Operations
and
CAP
pin, the device attempts an AutoStore
write
CC
pin drops below V
operations
CAP
AA
HZWE
pin from V
(read cycle 1). If the read
AA
after WE goes LOW.
CAP
are
SD
access time without
CAP
before the end of
SWITCH
pin. This stored
on page 16 for a
inhibited.
ACE
CC
pin, AutoStore
CAP
. A STORE
Preventing
or at t
, the part
capacitor.
0–7
CC
DOE
The
are
to
,
Figure 3
(V
Characteristics
the V
pull-up on WE to hold it inactive during power-up. This pull-up is
only effective if the WE signal is tristate during power-up. Many
MPUs tristate their controls on power-up. This must be verified
when using the pull-up. When the nvSRAM comes out of
power-on-recall, the MPU must be active or the WE held inactive
until the MPU comes out of reset.
To reduce unnecessary nonvolatile stores, AutoStore and
Hardware STORE operations are ignored unless at least one
write operation has taken place since the most recent STORE or
RECALL cycle. Software-initiated STORE cycles are performed
regardless of whether a write operation has taken place. The
HSB signal is monitored by the system to detect if an AutoStore
cycle is in progress.
Figure 3. AutoStore Mode
Hardware STORE Operation
The CY14B256LA provides the HSB pin to control and
acknowledge the STORE operations. Use the HSB pin to
request a Hardware STORE cycle. When the HSB pin is driven
LOW, the CY14B256LA conditionally initiates a STORE
operation after t
write to the SRAM has taken place since the last STORE or
RECALL cycle. The HSB pin also acts as an open drain driver
(internal 100 kΩ weak pull-up resistor) that is internally driven
LOW to indicate a busy condition when the STORE (initiated by
any means) is in progress.
Note After each Hardware and Software STORE operation HSB
is driven HIGH for a short time (t
current and then remains HIGH by internal 100 kΩ pull-up
resistor.
SRAM write operations that are in progress when HSB is driven
LOW by any means are given time (t
the STORE operation is initiated. However, any SRAM write
cycles requested after HSB goes LOW are inhibited until HSB
returns HIGH. In case the write latch is not set, HSB is not driven
LOW by the CY14B256LA. But any SRAM read and write cycles
are inhibited until HSB is returned HIGH by MPU or other
external source.
CAP
CAP
) for automatic STORE operation. Refer to
shows the proper connection of the storage capacitor
pin is driven to V
on page 9 for the size of V
DELAY
WE
. An actual STORE cycle only begins if a
CC
V
V
V
CC
CC
SS
by a regulator on the chip. Place a
HHHD
V
CAP
) with standard output high
DELAY
CY14B256LA
) to complete before
CAP
0.1 uF
. The voltage on
DC Electrical
Page 5 of 22
V
CAP
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