CS8422-DNZ Cirrus Logic Inc, CS8422-DNZ Datasheet - Page 54

• Manufacturer Part Number: CS8422-DNZ
• Description: IC 24-bit 192kHz SRC S/PDIF Receiver
• Manufacturer: Cirrus Logic Inc

54
11.12 Serial Audio Output Data Format - SDOUT1 (0Ch)
SOMS1
7
0
SIFSEL[2:0] - Serial audio input data format
SOMS1 - Master/Slave Mode Selector
SOSF1 - OSCLK1 Frequency. Valid only in master mode (SOMS1 = 1). If the SRC is selected as the source
for SDOUT1 (SDOUT1[1:0] = 00 in register 0Ah), then the master clock (MCLK) is the SAO MCLK (as se-
lected by the SAO_MCLK bit in register 08h). If the AES3 receiver is selected as the source for SDOUT1
(SDOUT1[1:0] = 01 in register 0Ah), then the MCLK is RMCK. Should be changed when PDN = 1. See
Table 9
SAI_CLK[3:0] determines the MCLK/OLRCK1 ratio.
000 - Left-Justified, up to 24-bit data
001 - I²S, up to 24-bit data
010 - Right-Justified, 24-bit data
011 - Right-Justified, 20-bit data
100 - Right-Justified, 18-bit data
101 - Right-Justified, 16-bit data
110, 111 - Reserved
0 - Serial audio output port is in slave mode. OSCLK and OLRCK are inputs.
1 - Serial audio output port is in master mode. OSCLK and OLRCK are outputs.
for details. Note: If serial output 1 is in master mode and sourced directly by the serial input port,
SOSF1
SAI_CLK[3:0], or
SAO_CLK[3:0],
6
0
RMCK[3:0]
0101
0110
1000
0000
0001
0010
0011
0100
0101
0110
1000
0111
0111
Table 9. OSCLK1/OLRCK1 Ratios and SOSF1 Settings
SORES1_1
Table 8. ISCLK/ILRCK Ratios and SISF Settings
5
0
MCLK/OLRCK1 Ratio
SORES1_0
4
0
1024
1024
384
512
768
128
192
256
384
512
768
64
96
SOFSEL1_1
3
0
SOSF1 = 0
OSCLK1/OLRCK1 Ratio
SOFSEL1_0
48
64
48
64
64
48
64
48
64
48
64
48
64
2
0
SOSF1 = 1
INVALID
128
128
128
128
128
128
TDM1
96
96
96
96
96
96
1
0
CS8422
DS692PP1
TDM0
0
0