CS8422-DNZ Cirrus Logic Inc, CS8422-DNZ Datasheet - Page 34

• Manufacturer Part Number: CS8422-DNZ
• Description: IC 24-bit 192kHz SRC S/PDIF Receiver
• Manufacturer: Cirrus Logic Inc

34
6.7.1
6.7.2
6.8
6.9
6.10
6.10.1 Hardware Mode Control
6.10.2 Software Mode Control
Format Detection (Software Mode Only)
In Software Mode, the CS8422 can automatically detect various serial audio input formats. The Format De-
tect Status register (12h) is used to indicate a detected format. The register will indicate if uncompressed
PCM data, IEC61937 data, DTS_LD data, DTS_CD data, or digital silence was detected. Additionally, the
IEC61937 Pc/Pd burst preambles are available in registers 2Dh-30h. See the register descriptions for more
information.
Interrupts (Software Mode Only)
The INT signal, available in Software Mode, indicates when an interrupt condition has occurred and may be
output on one of the GPOs. It can be set through bits INT[1:0] in the Control1 register (02h) to be active low,
active high, or open-drain active low. This last mode is used for active low, wired-OR hook-ups, with multiple
peripherals connected to the microcontroller interrupt input pin.
Many conditions can cause an interrupt, as listed in the interrupt status register descriptions. Each source
may be masked off through mask register bits. In addition, some sources may be set to rising edge, falling
edge, or level sensitive. Combined with the option of level sensitive or edge sensitive modes within the mi-
crocontroller, many different configurations are possible, depending on the needs of the equipment design-
er. Refer to the register descriptions for the Interrupt Unmasking (0Fh), Interrupt Mode (10h), and Interrupt
Status (14h) registers
Channel Status and User Data Handling
“Channel Status Buffer Management” on page 66
User data.
Hardware Mode Control
In Hardware Mode, AUDIO is output on the V/AUDIO pin when a 20 kΩ resistor is connected from the
V/AUDIO pin to VL.
Software Mode Control
In Software Mode, the AUDIO signal is available through the GPO pins. See
page 50
In Hardware Mode, Received Channel Status (C), and User (U) bits are output on the C and TX/U pins
(U data output must be selected on the TX/U pin, see
OLRCK2 and RCBL are made available to qualify the C and U data output.
the C and U data and their related signals.
In Software Mode, several options are available for accessing the Channel Status and User data that is
encoded in the received AES3 or SPDIF data.
The first option allows access directly through registers. The first 5 bytes of the Channel Status block are
decoded into the
data. Registers 28h-2Ch contain the B channel status data.
Received Channel Status (C), User (U), and EMPH bits may also be serial outputs to the GPO pins by
appropriately setting the GPOxSEL bits in the
for more details.
“Channel Status Registers (23h -
“GPO Control 1 (05h)”
describes the overall handling of Channel Status and
2Ch)”. Registers 23h-27h contain the A channel status
“Hardware Mode Control” on page 39
registers. OLRCK and RCBL can be
Figure 19
“GPO Control 1 (05h)” on
illustrates timing of
CS8422
for details).
DS692PP1