CS8422-DNZ Cirrus Logic Inc, CS8422-DNZ Datasheet - Page 18

• Manufacturer Part Number: CS8422-DNZ
• Description: IC 24-bit 192kHz SRC S/PDIF Receiver
• Manufacturer: Cirrus Logic Inc

18
Notes:
SDIN/TDM_IN Setup Time Before I/OSCLK Rising Edge
SDIN/TDM_IN Hold Time After I/OSCLK Rising Edge
TDM Mode OSCLK Frequency
TDM Mode OSCLK Falling Edge to OLRCK Edge
RMCK Output Frequency
MCLK_OUT Frequency
Slave Mode
ISCLK Frequency
ISCLK High Time
ISCLK Low Time
OSCLK Frequency
OSCLK High Time
OSCLK Low Time
I/OLRCK Edge to I/OSCLK Rising Edge
I/OSCLK Rising Edge to I/OLRCK Edge
OSCLK Falling Edge/OLRCK Edge to SDOUT Output
Valid
SDIN/TDM_IN Setup Time Before I/OSCLK Rising Edge
SDIN/TDM_IN Hold Time After I/OSCLK Rising Edge
TDM Mode OLRCK High Time
TDM Mode OLRCK Rising Edge to OSCLK Rising Edge
TDM Mode OSCLK Rising Edge to OLRCK Falling Edge
Master Mode
I/OSCLK Frequency (non-TDM Mode)
I/OLRCK Duty Cycle
I/OSCLK Duty Cycle
I/OSCLK Falling Edge to I/OLRCK Edge
OSCLK Falling Edge to SDOUT Output Valid
SDIN/TDM_IN Setup Time Before I/OSCLK Rising Edge
SDIN/TDM_IN Hold Time After I/OSCLK Rising Edge
TDM Mode OSCLK Frequency
TDM Mode OSCLK Falling Edge to OLRCK Edge
7. After powering up the CS8422, RST should be held low until the power supplies and clocks are settled.
8. If ISCLK is selected as the clock source for the PLL, then the Sample Rate = ISCLK/64.
Parameter
(Note 10)
(Note 11)
(Note 11)
VL = 1.8 V, 2.5 V
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
lrckh
sckh
sckh
t
t
t
t
sckl
sckl
lcks
lckd
dpd
t
t
lcks
dpd
t
t
fsm
fsm
fsh
fss
ds
dh
ds
dh
ds
dh
48*Fsi/o
28.7
28.7
Min
2.2
5.5
9.2
9.2
7.4
6.2
4.7
7.3
7.0
6.2
4.7
7.3
20
45
45
-
-
-
-
-
-
-
-
-
-
-
Typ
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
128*Fsi/o
49.152
49.152
Max
15.7
25.6
4.2
5.7
5.4
5.7
31
31
55
31
55
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
CS8422
DS692PP1
Units
MHz
MHz
MHz
MHz
MHz
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
%
%