CS5364-DQZR Cirrus Logic Inc, CS5364-DQZR Datasheet - Page 25
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CS5364-DQZR
Manufacturer Part Number
CS5364-DQZR
Description
IC,A/D CONVERTER,QUAD,24-BIT,QFP,48PIN
Manufacturer
Cirrus Logic Inc
DS625F2
4.7
MCLK Divider
MCLK (MHz)
SCLK (MHz)
MCLK/LRCK Ratio
SCLK/LRCK Ratio
MCLK Divider
MCLK (MHz)
SCLK (MHz)
MCLK/LRCK Ratio
SCLK/LRCK Ratio
MCLK Divider
MCLK (MHz)
SCLK (MHz)
MCLK/LRCK Ratio
SCLK/LRCK Ratio
MCLK Divider
MCLK (MHz)
SCLK (MHz)
MCLK/FS Ratio
SCLK/FS Ratio
MCLK Divider
MCLK (MHz)
SCLK (MHz)
MCLK/FS Ratio
SCLK/FS Ratio
LJ/I²S MASTER OR SLAVE
LJ/I²S MASTER OR SLAVE
LJ/I²S MASTER OR SLAVE
Master and Slave Clock Frequencies
Tables 4 through 12
MCLK/LRCK ratio should be kept at a constant value during each mode. In Master Mode, the device outputs
the frequencies shown. In Slave Mode, the SCLK/LRCK ratio can be set according to design preference.
However, device performance is guaranteed only when using the ratios shown in the tables.
Control Port Mode only
TDM MASTER
TDM SLAVE
Table 6. Frequencies for 192 kHz Sample Rate using LJ/I²S
Table 4. Frequencies for 48 kHz Sample Rate using LJ/I²S
Table 5. Frequencies for 96 kHz Sample Rate using LJ/I²S
Table 7. Frequencies for 48 kHz Sample Rate using TDM
Table 8. Frequencies for 48 kHz Sample Rate using TDM
show the clock speeds for sample rates of 48 kHz, 96 kHz and 192 kHz. The
49.152
49.152
49.152
12.288
49.152
12.288
49.152
12.288
3.072
6.144
1024
1024
1024
512
256
256
256
÷4
64
÷4
64
÷4
64
÷4
÷4
36.864
12.288
36.864
12.288
36.864
36.864
36.864
12.288
3.072
6.144
768
384
192
768
256
768
256
÷3
64
÷3
64
÷3
64
÷3
÷3
QSM Fs = 192 kHz
DSM Fs = 96 kHz
SSM Fs = 48 kHz
SSM Fs = 48 kHz
SSM Fs = 48 kHz
24.567
12.288
24.567
12.288
24.576
24.567
12.288
3.072
6.144
512
256
512
256
512
256
128
÷2
÷2
÷2
64
÷2
64
÷2
24
64
18.384
18.384
12.288
18.384
12.288
18.384
12.288
18.384
3.072
6.144
÷1.5
÷1.5
÷1.5
÷1.5
÷1.5
384
256
384
256
384
192
64
64
96
64
CS5364
12.288
12.288
12.288
12.288
12.288
12.288
12.288
12.288
3.072
6.144
256
256
256
256
256
128
÷1
÷1
÷1
64
÷1
64
÷1
64
64
25