CS5364-DQZR Cirrus Logic Inc, CS5364-DQZR Datasheet - Page 17
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CS5364-DQZR
Manufacturer Part Number
CS5364-DQZR
Description
IC,A/D CONVERTER,QUAD,24-BIT,QFP,48PIN
Manufacturer
Cirrus Logic Inc
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DS625F2
SWITCHING SPECIFICATIONS - CONTROL PORT - I²C TIMING
Inputs: Logic 0 = DGND, Logic 1 = VLC, SDA C
Notes:
SCL Clock Frequency
RST Rising Edge to Start
Bus Free Time Between Transmissions
Start Condition Hold Time (prior to first clock pulse)
Clock Low time
Clock High Time
Setup Time for Repeated Start Condition
SDA Hold Time from SCL Falling
SDA Setup time to SCL Rising
Rise Time of SCL and SDA
Fall Time SCL and SDA
Setup Time for Stop Condition
Acknowledge Delay from SCL Falling
1. Data must be held for sufficient time to bridge the transition time, t
R S T
S D A
S CL
Stop
t
Parameter
t
irs
buf
Sta rt
t
t
hdst
lo w
t
hdd
t
high
Figure 5. I²C Timing
L
(Note 1)
= 30 pF
t sud
t ack
Symbol
t
t
t
t
t
t
t
t
t
susp
f
hdst
high
sust
t
hdd
low
sud
t
ack
buf
t
scl
irs
rc
fc
Re p e at e d
t sust
Sta rt
Min
600
600
300
4.7
4.0
4.7
4.0
4.7
4.7
0
-
-
-
fc
t
hdst
, of SCL.
t rd
t rc
t fc
Max
1000
t fd
100
300
1
-
-
Stop
t susp
CS5364
Unit
kHz
ns
µs
µs
ns
µs
ns
µs
ns
17
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