CS2300CP-CZZ Cirrus Logic Inc, CS2300CP-CZZ Datasheet - Page 26

• Manufacturer Part Number: CS2300CP-CZZ
• Description: IC General Purpose PLL LCO
• Manufacturer: Cirrus Logic Inc
• Type: Fanout Distribution, Fractional N Synthesizerr

Specifications of CS2300CP-CZZ

• Pll: Yes
• Input: Clock
• Output: Clock
• Number Of Circuits: 1
• Ratio - Input:output: 1:2
• Differential - Input:output: No/No
• Frequency - Max: 75MHz
• Divider/multiplier: Yes/Yes
• Voltage - Supply: 3.1 V ~ 3.5 V
• Operating Temperature: -10°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 10-MSOP, Micro10™, 10-uMAX, 10-uSOP
• Frequency-max: 75MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1494 - BOARD EVAL GEN PURPOSE PLL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 598-1754; CS2300CP-CZZ

26
8.3.3
8.4
8.4.1
8.4.2
8.5
Reserved
LSB+15
MSB-8
LSB+7
MSB
7
7
Global Configuration (Address 05h)
Ratio (Address 06h - 09h)
These registers contain the User Defined Ratio as shown in the
page
Ratio Configuration” on page 16
Enable Device Configuration Registers 1 (EnDevCfg1)
This bit, in conjunction with EnDevCfg2 and EnDevCfg3, configures the device for control port mode.
These EnDevCfg bits can be set in any order and at any time during the control port access sequence,
however they must all be set before normal operation can occur.
Note:
Port” on page
Setting this bit allows writes to the Device Control and Device Configuration registers (address 02h - 04h)
but keeps them from taking effect until this bit is cleared.
Enable Device Configuration Registers 2 (EnDevCfg2)
This bit, in conjunction with EnDevCfg1 and EnDevCfg3, configures the device for control port mode.
These EnDevCfg bits can be set in any order and at any time during the control port access sequence,
however they must all be set before normal operation can occur.
Note:
Port” on page
EnDevCfg1
0
1
Application:
FREEZE
0
1
EnDevCfg2
0
1
Application:
Device Configuration Freeze (Freeze)
23. These 4 registers form a single 32-bit ratio value as shown above. See
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Reserved
EnDevCfg2 and EnDevCfg3 must also be set to enable control port mode. See
EnDevCfg1 and EnDevCfg3 must also be set to enable control port mode. See
6
6
20.
20.
Register State
Disabled.
Enabled.
“SPI / I²C Control Port” on page 20
Device Control and Configuration Registers
Register changes take effect immediately.
Modifications may be made to Device Control and Device Configuration registers (registers 02h-04h) without
the changes taking effect until after the FREEZE bit is cleared.
Register State
Disabled.
Enabled.
“SPI / I²C Control Port” on page 20
Reserved
5
5
and
“Calculating the User Defined Ratio” on page 29
Reserved
4
4
Freeze
3
3
Reserved
“Register Quick Reference” section on
2
2
“Output to Input Frequency
Reserved
1
1
for more details.
“SPI / I²C Control
“SPI / I²C Control
CS2300-CP
EnDevCfg2
MSB-15
MSB-7
LSB+8
DS843F1
LSB
0
0