CS2300CP-CZZR Cirrus Logic Inc, CS2300CP-CZZR Datasheet
CS2300CP-CZZR
Specifications of CS2300CP-CZZR
CS2300CP-CZZR
Available stocks
Related parts for CS2300CP-CZZR
CS2300CP-CZZR Summary of contents
Page 1
Fractional-N Clock Multiplier with Internal LCO Features Clock Multiplier / Jitter Reduction – Generates a Low Jitter MHz Clock from a Jittery or Intermittent MHz Clock Source Internal LC Oscillator for ...
Page 2
TABLE OF CONTENTS 1. PIN DESCRIPTION ................................................................................................................................. 4 2. TYPICAL CONNECTION DIAGRAM ..................................................................................................... 5 3. CHARACTERISTICS AND SPECIFICATIONS ...................................................................................... 6 RECOMMENDED OPERATING CONDITIONS .................................................................................... 6 ABSOLUTE MAXIMUM RATINGS ........................................................................................................ 6 DC ELECTRICAL CHARACTERISTICS ................................................................................................ 6 AC ELECTRICAL CHARACTERISTICS ................................................................................................ 7 ...
Page 3
Clock Skip Enable (ClkSkipEn) ............................................................................................. 27 8.6.2 AUX PLL Lock Output Configuration (AuxLockCfg) .............................................................. 27 8.6.3 Enable Device Configuration Registers 3 (EnDevCfg3) ........................................................ 27 8.7 Function Configuration 2 (Address 17h) ........................................................................................ 28 8.7.1 Enable PLL Clock Output on Unlock ...
Page 4
PIN DESCRIPTION VD GND CLK_OUT AUX_OUT CLK_IN Pin Name # Pin Description VD 1 Digital Power (Input) - Positive power supply for the digital and analog sections. GND 2 Ground (Input) - Ground reference. CLK_OUT 3 PLL Clock Output ...
Page 5
TYPICAL CONNECTION DIAGRAM 1 Note Notes: 1. Resistors 2 required for I C Ω operation. System MicroController Frequency Reference DS843F1 0.1 µF Ω SCL/CCLK SDA/CDIN AD0/CS CS2300-CP CLK_OUT CLK_IN FILTP 0.1 µF AUX_OUT FILTN ...
Page 6
CHARACTERISTICS AND SPECIFICATIONS RECOMMENDED OPERATING CONDITIONS GND = 0 V; all voltages with respect to ground. Parameters DC Power Supply Ambient Operating Temperature (Power Applied) Notes: 1. Device functionality is not guaranteed or implied outside of these limits. Operation ...
Page 7
AC ELECTRICAL CHARACTERISTICS Test Conditions (unless otherwise specified 3 3 pF. L Parameters Clock Input Frequency Clock Input Pulse Width Clock Skipping Timeout Clock Skipping Input Frequency PLL Clock Output Frequency ...
Page 8
PLL PERFORMANCE PLOTS Test Conditions (unless otherwise specified 3 12.288 MHz 12.288 MHz; Sample size = 10,000 points; Base Band Jitter (100 kHz); CLK_OUT CLK_IN AuxOutSrc[1:0] = 11. 10,000 ...
Page 9
CONTROL PORT SWITCHING CHARACTERISTICS- I²C FORMAT Inputs: Logic 0 = GND; Logic 1 = VD; C Parameter SCL Clock Frequency Bus Free-Time Between Transmissions Start Condition Hold Time (prior to first clock pulse) Clock Low Time Clock High Time Setup ...
Page 10
CONTROL PORT SWITCHING CHARACTERISTICS - SPI FORMAT Inputs: Logic 0 = GND; Logic 1 = VD; C Parameter CCLK Clock Frequency CCLK Edge to CS Falling CS High Time Between Transmissions CS Falling to CCLK Edge CCLK Low Time CCLK ...
Page 11
ARCHITECTURE OVERVIEW 4.1 Delta-Sigma Fractional-N Frequency Synthesizer The core of the CS2300 is a Delta-Sigma Fractional-N Frequency Synthesizer which has very high-resolu- tion for Input/Output clock ratios, low phase noise, very wide range of output frequencies and the ability ...
Page 12
Delta-Sigma Fractional-N Frequency Synthesizer LCO Digital PLL and Fractional-N Logic Frequency Reference Clock 12 Phase Internal Voltage Controlled Comparator Loop Filter Oscillator Fractional-N Divider Delta-Sigma Modulator N Digital Filter Frequency Comparator for Frac-N Generation Output to Input Ratio for Hybrid ...
Page 13
APPLICATIONS 5.1 Timing Reference Clock The internal LC oscillator is used to generate the internal timing reference clock (see Overview” on page 11 for information on how this internal clock is used by the CS2300). A single 0.1 µF ...
Page 14
Regardless of the setting of the ClkSkipEn bit the PLL output will continue for 2 634 ms) after CLK_IN is removed (see an effective change in period as the clock source is removed, otherwise the PLL will interpret this as ...
Page 15
If CLK_IN is removed and then re-applied within t continues while the PLL re-acquires lock (see moved the PLL output will continue until CLK_IN is re-applied at which point the PLL will go unlocked only for the time it takes ...
Page 16
Typically, applications in which the PLL_OUT signal creates a new clock domain from which all other sys- tem clocks and associated data are derived will benefit from the maximum jitter and wander rejection of the lowest PLL bandwidth setting. See ...
Page 17
LFRatioCfg bit, with 20.12 being the default. The R for high resolution (12.20) format is encoded with 12 MSBs representing the integer binary por- UD tion ...
Page 18
Ratio modifiers which would produce an overflow or truncation 1024 MOD 12.20 format. In all cases, the maximum and minimum allowable values for R quency limits for both the input and output ...
Page 19
PLL Clock Output The PLL clock output pin (CLK_OUT) provides a buffered version of the output of the frequency synthesizer. The driver can be set to high-impedance with the ClkOutDis bit. The output from the PLL automatically drives a ...
Page 20
Clock Output Stability Considerations 5.6.1 Output Switching CS2300 is designed such that re-configuration of the clock routing functions do not result in a partial clock period on any of the active outputs (CLK_OUT and/or AUX_OUT). In particular, enabling or ...
Page 21
The control port operates with either the SPI or I²C interface, with the CS2300 acting as a slave device. SPI Mode is selected if there is a high-to-low transition on the AD0/CS pin after power-up. I²C Mode is selected by ...
Page 22
SCL CHIP ADDRESS (WRITE AD0 0 SDA ACK START SCL CHIP ADDRESS (WRITE) SDA 1 0 ...
Page 23
Memory Address Pointer The Memory Address Pointer (MAP) byte comes after the address byte and selects the register to be read or written. Refer to the pseudocode above for implementation details. 6.3.1 Map Auto Increment The device has MAP ...
Page 24
REGISTER DESCRIPTIONS In I²C Mode all registers are read/write unless otherwise stated. In SPI mode all registers are write only. All “Re- served” registers must maintain their default state to ensure proper functional operation. The default state of each ...
Page 25
PLL Clock Output Disable (ClkOutDis) This bit controls the output driver for the CLK_OUT pin. ClkOutDis Output Driver State 0 CLK_OUT output driver enabled. 1 CLK_OUT output driver set to high-impedance. Application: “PLL Clock Output” on page 19 8.3 ...
Page 26
Enable Device Configuration Registers 1 (EnDevCfg1) This bit, in conjunction with EnDevCfg2 and EnDevCfg3, configures the device for control port mode. These EnDevCfg bits can be set in any order and at any time during the control port access ...
Page 27
Function Configuration 1 (Address 16h ClkSkipEn AuxLockCfg Reserved 8.6.1 Clock Skip Enable (ClkSkipEn) This bit enables clock skipping mode for the PLL and allows the PLL to maintain lock even when the CLK_IN has missing pulses. ClkSkipEn ...
Page 28
Function Configuration 2 (Address 17h Reserved Reserved Reserved 8.7.1 Enable PLL Clock Output on Unlock (ClkOutUnl) Defines the state of the PLL output during the PLL unlock condition. ClkOutUnl Clock Output Enable Status 0 Clock outputs are ...
Page 29
CALCULATING THE USER DEFINED RATIO Note: The software for use with the evaluation kit has built in tools to aid in calculating and converting the User Defined Ratio. This section is for those who are not interested in the ...
Page 30
DIMENSIONS 10L MSOP (3 mm BODY) PACKAGE DRAWING TOP VIEW INCHES DIM MIN 0.0295 b 0.0059 c 0.0031 D -- 0.1181 BSC E -- 0.1929 BSC E1 -- 0.1181 ...
Page 31
... Jitter performance specifications,” May 2007. 2. Philips Semiconductor, “The I²C-Bus Specification: Version 2,” Dec. 1998. http://www.semiconductors.philips.com DS843F1 Package Temp Range Container Pb-Free Grade 10L-MSOP Yes Commercial 10L-MSOP Yes - Yes - CS2300-CP Order# -10° to +70°C Rail CS2300CP-CZZ Tape and -10° to +70°C CS2300CP-CZZR Reel - - CDK2000-LCO 31 ...
Page 32
HISTORY Release F1 Updated Period Jitter specification in Added “PLL Performance Plots” section on page Updated use conditions for Updated Figure 10 on page Removed FsDetect and Auto R-Mod features per ER758rev2. Contacting Cirrus Logic Support For all product ...