CS2300CP-CZZ Cirrus Logic Inc, CS2300CP-CZZ Datasheet - Page 18

• Manufacturer Part Number: CS2300CP-CZZ
• Description: IC General Purpose PLL LCO
• Manufacturer: Cirrus Logic Inc
• Type: Fanout Distribution, Fractional N Synthesizerr

Specifications of CS2300CP-CZZ

• Pll: Yes
• Input: Clock
• Output: Clock
• Number Of Circuits: 1
• Ratio - Input:output: 1:2
• Differential - Input:output: No/No
• Frequency - Max: 75MHz
• Divider/multiplier: Yes/Yes
• Voltage - Supply: 3.1 V ~ 3.5 V
• Operating Temperature: -10°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 10-MSOP, Micro10™, 10-uMAX, 10-uSOP
• Frequency-max: 75MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1494 - BOARD EVAL GEN PURPOSE PLL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 598-1754; CS2300CP-CZZ

18
5.3.4
Ratio modifiers which would produce an overflow or truncation of R
if R
12.20 format. In all cases, the maximum and minimum allowable values for R
quency limits for both the input and output clocks as shown in the
page
Ratio Configuration Summary
The R
setting LFRatioCfg. R-Mod is applied if selected. The user defined ratio, and ratio modifier make up the
effective ratio R
diagram in
erate the fractional-N value which controls the Frequency Synthesizer.
Referenced Control
Ratio......................................“Ratio (Address 06h - 09h)” on page 26
LFRatioCfg
RModSel[2:0]
UD
User Defined Ratio R
7.
UD
is 1024 an R
is the user defined ratio stored in the register space. The resolution for the R
............................“Low-Frequency Ratio Configuration (LFRatioCfg)” on page 28
Ratio
Figure 15
........................“R-Mod Selection (RModSel[2:0])” section on page 25
EFF
UD
, the final calculation used to determine the output to input clock ratio. The conceptual
MOD
Effective Ratio R
summarizes the features involved in the calculation of the ratio values used to gen-
Ratio Format
Register Location
LFRatioCfg
of 8 would produce an R
12.20
20.12
Figure 15. Ratio Feature Summary
EFF
RModSel[2:0]
Modifier
Ratio
EFF
LCO
value of 8192 which exceeds the 4096 limit of the
Frequency Reference Clock
Fractional N Logic
Synthesizer
Frequency
Digital PLL &
(CLK_IN)
EFF
N
“AC Electrical Characteristics” on
should not be used; For example
EFF
are dictated by the fre-
PLL Output
UD
CS2300-CP
is selectable by
DS843F1