CRD42L51 Cirrus Logic Inc, CRD42L51 Datasheet - Page 69

• Manufacturer Part Number: CRD42L51
• Description: Ref Bd Low-voltage Stereo Codec
• Manufacturer: Cirrus Logic Inc

DS679F1
6.21
Note: The DATA_SEL[1:0] bits in reg09h must be set to ‘01’b to enable function control in this register.
LIMIT_EN
7
Limiter Release Rate Register (Address 1Ah)
Peak Detect and Limiter Enable (LIMIT_EN)
Default: 0
0 - Disabled
1 - Enabled
Function:
Limits the maximum signal amplitude to prevent clipping when this function is enabled. Peak Signal Limiting
is performed by digital attenuation. Note: When the limiter is enabled, the AOUT Volume is automatically
controlled and should not be adjusted manually. Alternative volume control may be realized using the
PCMMIXx_VOL[6:0] bits.
Peak Signal Limit All Channels (LIMIT_ALL)
Default: 1
0 - Individual Channel
1 - Both channel A & B
Function:
When set to 0, the peak signal limiter will limit the maximum signal amplitude to prevent clipping on the spe-
cific channel indicating clipping. The other channels will not be affected.
When set to 1, the peak signal limiter will limit the maximum signal amplitude to prevent clipping on both
channels in response to any single channel indicating clipping.
Limiter RELEASE Rate (RRATE[5:0])
Default: 111111
Function:
Sets the rate at which the limiter releases the digital attenuation from levels below the minimum setting in
the limiter threshold register, and returns the analog output level to the AOUTx_VOL[7:0] setting.
The limiter release rate is user selectable but is also a function of the sampling frequency, Fs, and the
DAC_SZC setting unless the disable bit is enabled.
Binary Code
000000
LIMIT_ALL
111111
···
6
RRATE5
5
Slowest Release
Fastest Release
Release Time
···
RRATE4
4
RRATE3
3
RRATE2
2
RRATE1
1
CS42L51
RRATE0
0
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