ADV7177KSZ-REEL Analog Devices Inc, ADV7177KSZ-REEL Datasheet - Page 10

• Manufacturer Part Number: ADV7177KSZ-REEL
• Description: IC,TV/VIDEO CIRCUIT,Color Encoder Circuit,CMOS,QFP,44PIN,PLASTIC
• Manufacturer: Analog Devices Inc
• Type: Video Encoderr

Specifications of ADV7177KSZ-REEL

• Applications: Set-Top Boxes, TV
• Voltage - Supply, Analog: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Package / Case: 44-MQFP, 44-PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Supply, Digital: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADV7177/ADV7178
3.3 V TIMING SPECIFICATIONS
V
Table 6.
Parameter
MPU PORT
ANALOG OUTPUTS
CLOCK CONTROL AND PIXEL PORT
RESET CONTROL
INTERNAL CLOCK CONTROL
OSD TIMING
1
2
3
4
5
6
The max/min specifications are guaranteed over this range.
Temperature range T
TTL input values are 0 V to 3 V, with input rise/fall times ≤ 3 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and outputs.
Analog output load ≤ 10 pF.
Guaranteed by characterization.
Output delay measured from the 50% point of the rising edge of CLOCK to the 50% point of full-scale transition.
Pixel port consists of the following:
Pixel inputs: P15–P0
Pixel controls: HSYNC , FIELD/ VSYNC , BLANK
Clock input: CLOCK
AA
SCLOCK Frequency
SCLOCK High Pulse Width, t
SCLOCK Low Pulse Width, t
Hold Time (Start Condition), t
Setup Time (Start Condition), t
Data Setup Time, t
SDATA, SCLOCK Rise Time, t
SDATA, SCLOCK Fall Time, t
Setup Time (Stop Condition), t
Analog Output Delay
DAC Analog Output Skew
f
Clock High Time, t
Clock Low Time, t
Data Setup Time, t
Data Hold Time, t
Control Setup Time, t
Control Hold Time, t
Digital Output Access Time, t
Digital Output Hold Time, t
Pipeline Delay, t
RESET Low Time
Clock/2 Rise Time, t
Clock/2 Fall Time, t
OSD Setup Time, t
OSD Hold Time, t
CLOCK
= 3.0 V–3.6 V,
3, 4
4
3, 4
1
15
MIN
3, 5
19
12
V
10
9
18
5
11
to T
17
REF
16
12
11
MAX
= 1.235 V, R
: 0°C to 70°C.
2
14
7
1
6
13
3
4
8
3, 4, 6
SET
= 300 Ω. All specifications T
Conditions
After this period the first clock is generated
Repeated for start condition
Rev. C | Page 10 of 44
MIN
to T
MAX
,
2
unless otherwise noted.
Min
0
4.0
4.7
4.0
4.7
250
4.7
8
8
3.5
4
4
3
6
Typ
7
0
27
4
37
10
10
10
2
Max
100
1
300
24
Unit
kHz
µs
µs
µs
µs
ns
µs
ns
µs
ns
ns
MHz
ns
ns
ns
ns
ns
ns
ns
ns
Clock cycles
ns
ns
ns
ns
ns