ADV611JSTZ Analog Devices Inc, ADV611JSTZ Datasheet
ADV611JSTZ
Specifications of ADV611JSTZ
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ADV611JSTZ Summary of contents
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FEATURES Programmable “Quality Box” Industrial Temperature Range (ADV612) Hardware Frame Rate Reduction 100% Bitstream Compatible with the ADV601 and ADV601LC Precise Compressed Bit Rate Control Field Independent Compression 8-Bit Video Interface Supports CCIR-656 and Multi- plexed Philips Formats General ...
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ADV611/ADV612 TABLE OF CONTENTS This data sheet gives an overview of the ADV611/ADV612’s functionality and provides details on designing the part into a system. The text of the data sheet is written for an audience with a general knowledge of ...
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Original Video Image PROGRAMMABLE QUALITY BOX VARIABLE CONTRAST BACKGROUND The ADV611/ADV612 are real-time compression integrated circuits designed for remote video surveillance or closed circuit television (CCTV) applications. The most important feature of these two devices is the “Quality Box.” With ...
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ADV611/ADV612 INTERNAL ARCHITECTURE The ADV611/ADV612 is composed of eight blocks. Three of these blocks are interface blocks and five are processing blocks. The interface blocks are the Digital Video I/O Port, the Host I/O Port and the external DRAM manager. ...
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ENCODE RUN LENGTH WAVELET PATH ADAPTIVE CODER & KERNEL QUANTIZER HUFFMAN FILTER BANK DECODE PATH Figure 4. Encode and Decode Paths References For more information on the terms, techniques and underlying principles referred to in this data sheet, you may ...
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ADV611/ADV612 Figure 6. Unfiltered Original Image (Analog Devices Corporate Offices, Norwood, Massachusetts) Figure 7. Modified Mallat Diagram of Image –6– REV. 0 ...
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LUMINANCE AND COLOR COMPONENTS (EACH SEPARATELY) HIGH LOW PASS IN PASS HIGH LOW PASS IN PASS IN BLOCK HIGH LOW HIGH PASS IN PASS IN PASS ...
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ADV611/ADV612 THE PROGRAMMABLE QUANTIZER This block quantizes the filtered image based on the response profile of the human visual system. In general, the human eye cannot resolve high frequencies in images to the same level of accuracy as lower frequencies. ...
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Table III. Typical Quantization of Mallat Data Block Data Mallat Bin Width Blocks Factors 39 0x007F 40 0x009A 41 0x009A 36 0x00BE 33 0x00BE 30 0x00E4 34 0x00E6 35 0x00E6 37 0x00E6 38 0x00E6 31 0x0114 32 0x0114 27 0x0281 ...
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ADV611/ADV612 REGISTER ADDRESS BYTE 3 0x0 0x4 0x8 0xC INDIRECT (INTERNALLY INDEXED) REGISTERS {ACCESS THESE REGISTERS THROUGH THE INDIRECT REGISTER ADDRESS AND INDIRECT REGISTER DATA REGISTERS} *NOTE: YOU MUST WRITE 0X0880 TO THE MODE CONTROL REGISTER ON CHIP RESET TO ...
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ADV611/ADV612 REGISTER DESCRIPTIONS Indirect Address Register Direct (Write) Register Byte Offset 0x00. This register holds a 16-bit value (index) that selects the indirect register accessible to the host through the indirect data register. All indirect write registers are 16 bits ...
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ADV611/ADV612 [5] FIFO Stop, FIFOSTP. This condition indicates that the FIFO is full in decode mode and empty in encode mode. In decode mode only, FIFOSTP status actually behaves more conservatively than this. In decode mode, even when FIFOSTP is ...
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Video Interface Encode/Decode Mode Select, E/D. This bit selects the following: 0 Decode mode video interface (compressed-to-raw) 1 Encode mode video interface (raw-to-compressed), reset value [8] Reserved (always write zero) [9] Video Interface Bipolar/Unipolar Color Component Select, BUC. This ...
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ADV611/ADV612 VIDEO AREA REGISTERS When the quality box is disabled (Mode Control register, Bit 14 = 0), the area defined by the HSTART, HEND, VSTART and VEND registers is the active area that the wavelet kernel processes. Video data outside ...
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To vertically crop video while encoding, program the VSTART and VEND registers with actual video line numbers, which differ for each field. The VSTART and VEND contents must be updated on each field, unless the quality box is enabled. Perform ...
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ADV611/ADV612 Sum of Luma Value Register Indirect (Read Only) Register Index 0x0AA The Sum of Luma Value register lets the host or DSP read the sum of pixel values for the Luma component in block 39. The Host reads these ...
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MIN Cr Value Register Indirect (Read Only) Register Index 0x0B1 The MIN Cr Value register lets the host or DSP read the minimum pixel value for the Cr component in the unprocessed data. The Host reads these values through the ...
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ADV611/ADV612 Clock Pins Name Pins I/O VCLK/XTAL 2 I VCLKO 1 O Video Interface Pins Name Pins I/O VSYNC HSYNC FIELD ENC 1 O VDATA[7:0] 8 I/O STALL ...
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DRAM Interface Pins Name Pins I/O DDAT[15:0] 16 I/O DADR[8: RAS 1 O CAS Host Interface Pins Name Pins I/O DATA[31:0] 32 I/O ADR[1: BE0–BE1 2 I BE2–BE3 ...
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ADV611/ADV612 Host Interface Pins (Continued) Name Pins I/O ACK 1 O FIFO_SRQ 1 O STATS_R 1 O LCODE 1 O HIRQ 1 O RESET 1 I Power Supply Pins Name Pins I/O GND 16 I VDD 13 I Description Host ...
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Video Interface The ADV611/ADV612 video interface supports two types of component digital video (D1) interfaces in both compression (input) and decompression (output) modes. These digital video interfaces include support for the Multiplexed Philips 4:2:2 and CCIR-656/SMPTE125M—international standard. Video interface master ...
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ADV611/ADV612 Bit/ Name Component CCIR-656 8 Multiplex Philips 8 Clocks and Strobes All video data is synchronous to the video clock (VCLK). The rising edge of VCLK is used to clock all data into the ADV611/ADV612. Synchronization and Blanking Pins ...
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Table X. Philips Multiplexed Video Master and Slave Modes HSYNC, VSYNC, and FIELD Functionality HSYNC, VSYNC and FIELD Functionality for Multiplexed Master Mode (HSYNC, VSYNC Philips and FIELD Are Outputs) Encode Mode (video data is input The ADV611/ADV612 completely manages ...
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ADV611/ADV612 Compressed Data-Stream Definition Through its Host Interface the ADV611/ADV612 outputs (dur- ing encode) and receives (during decode) compressed digital video data. This stream of data passing between the ADV611/ ADV612 and the host is hierarchically structured and broken up ...
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Table XII. Pseudo-Code Describing a Sequence of Video Fields Complete Sequence: <Field 1 Sequence> <Field 2 Sequence> <Field 1 Sequence> <Field 2 Sequence> (Field Sequences) <Field 1 Sequence> <Field 2 Sequence> #EOS Field 1 Sequence: #SOF1 <VITC> <First Block Sequence> ...
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ADV611/ADV612 In general, a Frame of data is made up of odd and even Fields as shown in Figure 13. Each Field Sequence is made First Block Sequence and a Complete Block Sequence. The First Block Sequence ...
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Table XIII. Pseudo Code of Compressed Video Data Bitstream for One Field of Video Block Sequence Data #SOFn<VITC><TYPE4><BW><Huff_Data> #SOB4<BW><Huff_Data> #SOB3<BW><Huff_Data> #SOB3<BW><Huff_Data> #SOB3<BW><Huff_Data> #SOB3<BW><Huff_Data> #SOB3<BW><Huff_Data> #SOB3<BW><Huff_Data> #SOB3<BW><Huff_Data> #SOB3<BW><Huff_Data> #SOB3<BW><Huff_Data> #SOB3<BW><Huff_Data> #SOB3<BW><Huff_Data> #SOB3<BW><Huff_Data> #SOB3<BW><Huff_Data> #SOB1<BW><Huff_Data> #SOB3<BW><Huff_Data> #SOB1<BW><Huff_Data> #SOB3<BW><Huff_Data> #SOB1<BW><Huff_Data> #SOB3<BW><Huff_Data> #SOB1<BW><Huff_Data> #SOB3<BW><Huff_Data> ...
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ADV611/ADV612 Table XV. ADV611/ADV612 Field and Block Delimiters (Codes) Code Name Code #SOF1 0xffffffff40000000 #SOF2 0xffffffff41000000 <VITC> (96 bits) <TYPE1> 0x81 <TYPE2> 0x82 <TYPE3> 0x83 <TYPE4> 0x84 #SOB1 0xffffffff81 #SOB2 0xffffffff82 #SOB3 0xffffffff83 #SOB4 0xffffffff84 #SOB5 0xffffffff8f <BW> (16 bits, ...
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Table XVI. Video Data Bitstream for One Field In a Video Sequence ffff ffff 4000 0000 0000 8400 00ff df0c daff ffff ffff ffff 8300 00ff 609f 609f ffff ffff ffff 8300 8300 00fe c70f ffff ffff ffff ffff 8300 ...
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ADV611/ADV612 APPLYING THE ADV611/ADV612 This section includes the following topics: • Using the ADV611/ADV612 in computer applications • Using the ADV611/ADV612 in stand-alone applications • Configuring the host interface for 16- or 32-bit data paths • Connecting the video interface ...
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FL0 FL1 D8–D23 ADSP-2185 PF4 PF5 FL2 RD WR IRQ2 IRQL1 THE ADSP-2185 INTERNAL CLOCK RATE DOUBLE THE INPUT CLOCK *THE INPUT CLOCK RATE = 1/2 OF THE INTERNAL CLOCK RATE, RANGING FROM 12 TO 21MHz Figure 16. Alternate Stand-Alone ...
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ADV611/ADV612 8 P8–P15 HARRIS 8115 CLK2 CLK2 27MHz PIXEL CLOCK GSC Figure 20. Using the Harris 8115 Decoder GETTING THE MOST OUT OF ADV611/ADV612 How Much Compression Can Be Expected The ADV611/ADV612 can be used in applications where up to ...
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SPECIFICATIONS The ADV611/ADV612 Video Codec uses a Bi-Orthogonal (7, 9) Wavelet Transform. RECOMMENDED OPERATING CONDITIONS Parameter Description V Supply Voltage DD T Ambient Operating Temperature AMB ELECTRICAL CHARACTERISTICS Parameter Description V Hi-Level Input Voltage IH V Lo-Level Input Voltage IL ...
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ADV611/ADV612 TEST CONDITIONS Figure 22 shows test condition voltage reference and device loading information. These test conditions consider an output as disabled when the output stops driving and goes from the measured high or low voltage to a high impedance ...
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VCLK (O) VCLKO (VCLK2 = 0) (I) VCLKO (VCLK2 = 1) NOTE: USE VCLK FOR CLOCKING VIDEO-ENCODE OPERATIONS AND USE VCLKO FOR CLOCKING VIDEO-DECODE OPERATIONS. DO NOT TRY TO USE EITHER CLOCK FOR BOTH ENCODE AND DECODE. CCIR-656 Video ...
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ADV611/ADV612 Figure 26. CCIR-656 Video—Line (Horizontal) and Frame (Vertical) Transfer Timing Note that for CCIR-656 Video—Decode and Master Line (Horizontal) timing, VDATA is synchronous with VCLKO. –36– REV. 0 ...
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Multiplexed Philips Video Timing The diagrams in this section show transfer timing for pixel (YCrCb) data in Multiplexed Philips video mode. For line (horizontal) and frame (vertical) data transfer timing, see Figure 29. All output values assume a maximum pin ...
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ADV611/ADV612 Figure 29. Multiplexed Philips Video–Line (Horizontal) and Frame (Vertical) Transfer Timing –38– REV. 0 ...
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Table XXIV. Multiplexed Philips Video—Encode and Master Pixel (YCrCb) Timing Parameters Parameter Description t VDATA Bus, Encode Master Multiplexed Philips, Setup VDATA_EMM_S t VDATA Bus, Encode Master Multiplexed Philips, Hold VDATA_EMM_H t CTRL Signals, Encode Master Multiplexed Philips, Delay CTRL_EMM_D ...
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ADV611/ADV612 Host Interface (Indirect Address, Indirect Register Data and Interrupt Mask/Status) Register Timing The diagrams in this section show transfer timing for host read and write accesses to all of the ADV611/ADV612’s direct registers, except the Compressed Data register. Accesses ...
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Table XXVII. Host (Indirect Address, Indirect Data and Interrupt Mask/Status) Write Timing Parameters Parameter Description WR Signal, Direct Register, Write Cycle Time (at 27 MHz VCLK) t WR_D_WRC WR Signal, Direct Register, Pulsewidth Asserted (at 27 MHz VCLK) t WR_D_PWA ...
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ADV611/ADV612 Host Interface (Compressed Data) Register Timing The diagrams in this section show transfer timing for host read and write transfers to the ADV611/ADV612’s Compressed Data register. Accesses to the Compressed Data register are faster than access timing for the ...
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Table XXIX. Host (Compressed Data) Write Timing Parameters Parameter Description WR Signal, Compressed Data Direct Register, Write Cycle Time t WR_CD_WRC WR Signal, Compressed Data Direct Register, Pulsewidth Asserted t WR_CD_PWA WR Signal, Compressed Data Direct Register, Pulsewidth Deasserted t ...
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ADV611/ADV612 Pin Pin Pin Name Type 1 DATA4 I/O 2 DATA3 I/O 3 DATA2 I/O 4 DATA1 I/O 5 DATA0 I/O 6 VDD POWER 7 GND GROUND ADR1 I 12 ...
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DATA4 1 PIN 1 DATA3 2 IDENTIFIER DATA2 3 DATA1 4 DATA0 5 6 VDD 7 GND ADR1 ADR0 12 13 GND BE2–BE3 14 BE0–BE1 15 GND 16 RESET 17 18 VDD ACK ...
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ADV611/ADV612 0.030 (0.75) 0.024 (0.60) 0.020 (0.50) COPLANARITY 0.003 (0.08) Part Number Ambient Temperature Range ADV611JST + ADV612BST – +85 C NOTES Commercial temperature range ( +70 C). ...