ADUC7033BSTZ-88-RL Analog Devices Inc, ADUC7033BSTZ-88-RL Datasheet - Page 34

• Manufacturer Part Number: ADUC7033BSTZ-88-RL
• Description: Flash 96k ARM7 Dual 16-Bit ADC LIN I.C.
• Manufacturer: Analog Devices Inc
• Type: Battery Managementr

Specifications of ADUC7033BSTZ-88-RL

• Input Type: Logic
• Output Type: Logic
• Interface: UART, SPI
• Current - Supply: 20mA
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADuC7033
ADuC7033 KERNEL
The ADuC7033 features an on-chip kernel resident in the top
2 kB of the Flash/EE code space. After any reset event, this
kernel copies the factory calibrated data from the manufacturing
data space into the various on-chip peripherals. The peripherals
calibrated by the kernel are as follows:
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User MMRs that can be modified by the kernel and differ from
their POR default values are as follows:
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Power supply monitor (PSM)
Precision oscillator
Low power oscillator
REG_AVDD/REG_DVDD
Low power voltage reference
Normal mode voltage reference
Current ADC (offset and gain)
Voltage/temperature ADC (offset and gain)
R0 to R15
GP0CON/GP2CON
SYSCHK
ADCMDE/ADC0CON
FEE0ADR/FEE0CON/FEE0SIG
HVDAT/HVCON
HVCFG0/HVCFG1
T3LD
Rev. B | Page 34 of 140
The ADuC7033 also features an on-chip LIN downloader.
A flowchart of the execution of the kernel is shown in Figure 15.
The current revision of the kernel can be derived from
SYSSER1, as described in Table 100.
For the duration of the kernel execution, the watchdog timer is
active with a timeout period of 30 ms. This ensures that when
an error occurs in the kernel, the ADuC7033 automatically
resets. After a POR reset, the watchdog timer is disabled once
the kernel code is exited. After any other reset, the watchdog
timer maintains user code configuration for the period of the
kernel, and is refreshed just prior to kernel exit. A minimum
watchdog period of 30 ms is required. If LIN download mode is
entered, the watchdog is periodically refreshed.
Normal kernel execution time, excluding LIN download, is
approximately 5 ms. It is only possible to enter and leave LIN
download mode through a reset.
SRAM is not modified during normal kernel execution; rather,
SRAM is modified during a LIN download kernel execution.
Note that even with NTRST = 0, user code is not executed
unless Address 0x14 contains either 0x27011970 or the
checksum of Page 0, excluding Address 0x14. If Address 0x14
does not contain this information, user code is not executed
and LIN download mode is entered.
With NTRST = 1, user code is always executed.
During kernel execution, JTAG access is disabled.