ADUC7033BSTZ-88-RL Analog Devices Inc, ADUC7033BSTZ-88-RL Datasheet - Page 102

• Manufacturer Part Number: ADUC7033BSTZ-88-RL
• Description: Flash 96k ARM7 Dual 16-Bit ADC LIN I.C.
• Manufacturer: Analog Devices Inc
• Type: Battery Managementr

Specifications of ADUC7033BSTZ-88-RL

• Input Type: Logic
• Output Type: Logic
• Interface: UART, SPI
• Current - Supply: 20mA
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADuC7033
High Voltage Configuration0 Register
Name:
Address:
Default Value:
Access:
Function:
Table 74. HVCFG0 Bit Designations
Bit
7
6
5
4
3
2
1 to 0
HVCFG0
Indirectly addressed via the HVCON high voltage interface
0x00
Read/write
This 8-bit register controls the function of high voltage circuits on the ADuC7033. This register is not an MMR and
does not appear in the MMR memory map. It is accessed via the HVCON registered interface. Data to be written to
this register is loaded via the HVDAT MMR, and data is read back from this register via the HVDAT MMR.
Description
Wake/STI Thermal Shutdown Disable.
Set to 1 to disable the automatic shutdown of the wake/STI driver when a thermal event occurs.
Cleared to 0 to enable the automatic shutdown of the wake/STI driver when a thermal event occurs.
Precision Oscillator Enable Bit.
Set to 1 to enable the precision, 131 kHz oscillator. The oscillator start-up time is typically 70 μs (including high voltage
interface latency of 10 μs).
Cleared to 0 to power down the precision, 131 kHz oscillator.
Bit Serial Device (BSD) Mode Enable Bit.
Cleared to 0 to enable an internal (LIN) pull-up resistor on the LIN/BSD pin.
Set to 1 to disable the internal (LIN) pull-up and configure the LIN/BSD pin for BSD operation.
Wake Up (WU) Assert Bit.
Set to 1 to assert the external WU pin high.
Cleared to 0 to pull the external WU pin low via an internal 10 kΩ pull-down resistor.
Power Supply Monitor (PSM) Enable Bit.
Cleared to 0 to disable the power supply (voltage at the VDD pin) monitor.
Set to 1 to enable the power supply (voltage at the VDD pin) monitor. If the voltage at the VDD pin drops below 6.0 V
while IRQ3 (IRQEN[16]) is enabled, the PSM generates an interrupt.
Low Voltage Flag (LVF) Enable Bit.
Cleared to 0 to disable the LVF function.
Set to 1 to enable the LVF function. The low voltage flag can be interrogated via HVMON[3] after power up to
determine if the REG_DVDD voltage previously dropped below 2.1 V.
LIN Operating Mode. These bits enable/disable the LIN driver.
00 = LIN disabled.
01 = reserved (not LIN 2.0 compliant).
10 = LIN enabled.
11 = reserved, not used.
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