ADSP-21262SBBC-150 Analog Devices Inc, ADSP-21262SBBC-150 Datasheet - Page 36

• Manufacturer Part Number: ADSP-21262SBBC-150
• Description: IC,DSP,32-BIT,CMOS,BGA,136PIN,PLASTIC
• Manufacturer: Analog Devices Inc
• Series: SHARC®r
• Type: Fixed/Floating Pointr

Specifications of ADSP-21262SBBC-150

• Interface: DAI, SPI
• Clock Rate: 150MHz
• Non-volatile Memory: ROM (512 kB)
• On-chip Ram: 256kB
• Voltage - I/o: 3.30V
• Voltage - Core: 1.20V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 136-CSPBGA
• Device Core Size: 32/40Bit
• Architecture: Super Harvard
• Format: Floating Point
• Clock Freq (max): 150MHz
• Mips: 150
• Device Input Clock Speed: 150MHz
• Ram Size: 256KB
• Program Memory Size: 512KB
• Operating Supply Voltage (typ): 1.2/3.3V
• Operating Supply Voltage (min): 1.14/3.13V
• Operating Supply Voltage (max): 1.26/3.47V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 136
• Package Type: CSPBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

ADSP-21262
JTAG Test Access Port and Emulation
See
Table 31. JTAG Test Access Port and Emulation
1
2
Parameter
Timing Requirements
t
t
t
t
t
t
Switching Characteristics
t
t
System Inputs = AD15–0, SPIDS, CLKCFG1–0, RESET, BOOTCFG1–0, MISO, MOSI, SPICLK, DAI_Px, FLAG3–0.
System Outputs = MISO, MOSI, SPICLK, DAI_Px, AD15–0, RD, WR, FLAG3–0, CLKOUT, EMU, ALE.
TCK
STAP
HTAP
SSYS
HSYS
TRSTW
DTDO
DSYS
CPHASE = 1
CPHASE = 0
Table 31
(OUTPUT)
(OUTPUT)
(CP = 0)
(CP = 1)
(INPUT)
(INPUT)
(INPUT)
SPICLK
(INPUT)
SPICLK
(INPUT)
SPIDS
MISO
MOSI
MISO
MOSI
and
t
S D S C O
t
Figure
TCK Period
TDI, TMS Setup Before TCK High
TDI, TMS Hold After TCK High
System Inputs Setup Before TCK High
System Inputs Hold After TCK High
TRST Pulse Width
TDO Delay from TCK Low
System Outputs Delay After TCK Low
t
t
D S O E
D S O E
D S O V
27.
t
t
S P IC H S
S S P I D S
t
t
D D S P I D S
MSB VALID
S P I C L S
MSB VALID
MSB
MSB
t
D D S P I D S
Rev. B | Page 36 of 48 | August 2005
1
t
t
S P I C H S
Figure 26. SPI Protocol—Slave
S P I C L S
2
1
t
S S P I D S
t
D D S P I D S
LSB VALID
t
t
S P I C L K S
S S P I D S
t
H D S P I D S
LSB
LSB VALID
t
H S P I D S
Min
20
5
6
7
8
4t
CK
t
H S P I D S
t
H D S
LSB
t
S D P P W
Max
7
10
t
t
t
D S D H I
H D S P I D S
D S D H I
Unit
ns
ns
ns
ns
ns
ns
ns
ns