ADSP-21261SKBCZ150 Analog Devices Inc, ADSP-21261SKBCZ150 Datasheet - Page 19

• Manufacturer Part Number: ADSP-21261SKBCZ150
• Description: 150 MHz, 32Bit DSP Processor
• Manufacturer: Analog Devices Inc
• Series: SHARC®r
• Type: Fixed/Floating Pointr

Specifications of ADSP-21261SKBCZ150

• Interface: DAI, SPI
• Clock Rate: 150MHz
• Non-volatile Memory: ROM (384 kB)
• On-chip Ram: 128kB
• Voltage - I/o: 3.30V
• Voltage - Core: 1.20V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 136-CSPBGA
• Device Core Size: 32/40Bit
• Architecture: Super Harvard
• Format: Floating Point
• Clock Freq (max): 150MHz
• Mips: 150
• Device Input Clock Speed: 150MHz
• Ram Size: 128KB
• Program Memory Size: 384KB
• Operating Supply Voltage (typ): 1.2/3.3V
• Operating Supply Voltage (min): 1.14/3.13V
• Operating Supply Voltage (max): 1.26/3.47V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 136
• Package Type: CSPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Clock Input
See
Table 10. Clock Input
1
2
3
Clock Signals
The ADSP-21261 can use an external clock or a crystal. See
CLKIN pin description. The programmer can configure the
ADSP-21261 to use its internal clock generator by connecting
the necessary components to CLKIN and XTAL.
the component connections used for a crystal operating in fun-
damental mode. Note that the 150 MHz clock rate is achieved
using a 9.375 MHz crystal and a PLL multiplier ratio 16:1
(CCLK:CLKIN).
Parameter
Timing Requirements
t
t
t
t
t
Applies only for CLKCFG1
Applies only for CLKCFG1
Any changes to PLL control bits in the PMCTL register must meet core clock timing specification t
CK
CKL
CKH
CKRF
CCLK
CLKIN
NOTE: C1 AND C2 ARE SPECIFIC TO CRYSTAL SPECIFIED FOR X1.
CONTACT CRYSTAL MANUFACTURER FOR DETAILS. CRYSTAL
SELECTION MUST COMPLY WITH CLKCFG1–0 = 10 OR = 01.
Table 10
C1
CLKIN
Figure 8. 150 MHz Operation with a 9.375 MHz
and
Figure
Fundamental Mode Crystal
CLKIN Period
CLKIN Width Low
CLKIN Width High
CLKIN Rise/Fall (0.4 V–2.0 V)
CCLK Period
–
–
1M
X1
Figure 7. Clock Input
0 = 00 and default values for PLL control bits in PMCTL.
0 = 01 and default values for PLL control bits in PMCTL.
t
7.
CKH
C2
3
XTAL
t
CK
t
CKL
Figure 8
Rev. 0 | Page 19 of 44 | March 2006
shows
CCLK
Min
20
7.5
7.5
6.66
.
1
1
1
Max
160
80
80
3
10
2
2
2
ADSP-21261
Unit
ns
ns
ns
ns
ns