ADSP-21061KSZ-133 Analog Devices Inc, ADSP-21061KSZ-133 Datasheet - Page 11

• Manufacturer Part Number: ADSP-21061KSZ-133
• Description: ADSP-21061 1MBIT, 33MHz, 5v SHARC
• Manufacturer: Analog Devices Inc
• Series: SHARC®r
• Type: Floating Pointr

Specifications of ADSP-21061KSZ-133

• Interface: Synchronous Serial Port (SSP)
• Clock Rate: 33MHz
• Non-volatile Memory: External
• On-chip Ram: 128kB
• Voltage - I/o: 5.00V
• Voltage - Core: 5.00V
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 240-MQFP, 240-PQFP
• Package: 240MQFP
• Numeric And Arithmetic Format: Floating-Point
• Maximum Speed: 33 MHz
• Ram Size: 128 KB
• Device Million Instructions Per Second: 33 MIPS
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 2. Pin Descriptions (Continued)
Pin
ACK
SBTS
IRQ
FLAG
TIMEXP
HBR
HBG
CS
REDY
DMAR
DMAG
BR
ID2–0
RPBA
CPA
DTx
DRx
TCLKx
RCLKx
A = Asynchronous, G = Ground, I = Input, O = Output, P = Power Supply, S = Synchronous, (A/D) = Active Drive, (O/D) = Open-Drain,
T = Three-State (when SBTS is asserted, or when the ADSP-21061 is a bus slave)
6–1
2–0
3–0
2–1
2–1
Type
I/O/S
I/S
I/A
I/O/A
O
I/A
I/O
I/A
O (O/D)
I/A
O/T
I/O/S
O (O/D)
I/S
I/O (O/D)
O
I
I/O
I/O
Function
Memory Acknowledge. External devices can deassert ACK (low) to add wait states to an external memory
access. ACK is used by I/O devices, memory controllers, or other peripherals to hold off completion of an
external memory access. The ADSP-21061 deasserts ACK as an output to add wait states to a synchronous
access of its internal memory. In a multiprocessing system, a slave ADSP-21061 deasserts the bus master’s
ACK input to add wait state(s) to an access of its internal memory. The bus master has a keeper latch on its
ACK pin that maintains the input at the level to which it was last driven.
Suspend Bus Three-State. External devices can assert SBTS (low) to place the external bus address, data,
selects, and strobes in a high impedance state for the following cycle. If the ADSP-21061 attempts to access
external memory while SBTS is asserted, the processor halts and the memory access is not complete until
SBTS is deasserted. SBTS should only be used to recover from host processor/ADSP-21061 deadlock, or used
with a DRAM controller.
Interrupt Request Lines. May be either edge-triggered or level-sensitive.
Flag Pins. Each is configured via control bits as either an input or output. As an input, they can be tested as
a condition. As an output, they can be used to signal external peripherals.
Timer Expired. Asserted for four cycles when the timer is enabled and TCOUNT decrements to zero.
Host Bus Request. This pin must be asserted by a host processor to request control of the ADSP-21061’s
external bus. When HBR is asserted in a multiprocessing system, the ADSP-21061 that is bus master will
relinquish the bus and assert HBG. To relinquish the bus, the ADSP-21061 places the address, data, select,
and strobe lines in a high impedance state. HBR has priority over all ADSP-21061 bus requests BR
multiprocessing system.
Host Bus Grant. Acknowledges a bus request, indicating that the host processor may take control of the
external bus. HBG is asserted (held low) by the ADSP-21061 until HBR is released. In a multiprocessing system,
HBG is output by the ADSP-21061 bus master and is monitored by all others.
Chip Select. Asserted by host processor to select the ADSP-21061.
Host Bus Acknowledge. The ADSP-21061 deasserts REDY (low) to add wait states to an asynchronous access
of its internal memory or IOP registers by a host. This pin is an open-drain output (O/D) by default; it can be
programmed in the ADREDY bit of the SYSCON register to be active drive (A/D). REDY will only be output if
the CS and HBR inputs are asserted.
DMA Request 1 (DMA Channel 7) and DMA Request 2 (DMA Channel 6).
DMA Grant 1 (DMA Channel 7) and DMA Grant 2 (DMA Channel 6).
Multiprocessing Bus Requests. Used by multiprocessing ADSP-21061 processors to arbitrate for bus
mastership. An ADSP-21061 only drives its own BRx line (corresponding to the value of its ID2-0 inputs) and
monitors all others. In a multiprocessor system with less than six ADSP-21061s, the unused BRx pins should
be pulled high; the processor’s own BRx line must not be pulled high or low because it is an output.
Multiprocessing ID. Determines which multiprocessing bus request (BR1– BR6) is used by ADSP-21061.
ID = 001 corresponds to BR1, ID = 010 corresponds to BR2, etc., ID = 000 in single-processor systems. These
lines are a system configuration selection which should be hardwired or changed at reset only.
Rotating Priority Bus Arbitration Select. When RPBA is high, rotating priority for multiprocessor bus
arbitration is selected. When RPBA is low, fixed priority is selected. This signal is a system configuration
selection which must be set to the same value on every ADSP-21061. If the value of RPBA is changed during
system operation, it must be changed in the same CLKIN cycle on every ADSP-21061.
Core Priority Access. Asserting its CPA pin allows the core processor of an ADSP-21061 bus slave to interrupt
background DMA transfers and gain access to the external bus. CPA is an open-drain output that is
connected to all ADSP-21061s in the system. The CPA pin has an internal 5 kΩ pull-up resistor. If core access
priority is not required in a system, the CPA pin should be left unconnected.
Data Transmit (Serial Ports 0, 1). Each DT pin has a 50 kΩ internal pull-up resistor.
Data Receive (Serial Ports 0, 1). Each DR pin has a 50 kΩ internal pull-up resistor.
Transmit Clock (Serial Ports 0, 1). Each TCLK pin has a 50 kΩ internal pull-up resistor.
Receive Clock (Serial Ports 0, 1). Each RCLK pin has a 50 kΩ internal pull-up resistor.
Rev. C | Page 11 of 56 | July 2007
ADSP-21061/ADSP-21061L
6–1
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