ADSP-21060CZ-160 Analog Devices Inc, ADSP-21060CZ-160 Datasheet - Page 41
![Digital Signal Processor IC](/photos/6/71/67197/qs-240-2_sml.jpg)
ADSP-21060CZ-160
Manufacturer Part Number
ADSP-21060CZ-160
Description
Digital Signal Processor IC
Manufacturer
Analog Devices Inc
Series
SHARC®r
Type
Floating Pointr
Datasheet
1.ADSP-21062KSZ-133.pdf
(64 pages)
Specifications of ADSP-21060CZ-160
Peak Reflow Compatible (260 C)
No
Supply Voltage Max
5.25V
Dsp Type
Fixed / Floating Point
Leaded Process Compatible
No
Mounting Type
Surface Mount
Package / Case
240-MQFP
Interface
Host Interface, Link Port, Serial Port
Clock Rate
40MHz
Non-volatile Memory
External
On-chip Ram
512kB
Voltage - I/o
5.00V
Voltage - Core
5.00V
Operating Temperature
-40°C ~ 100°C
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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Part Number:
ADSP-21060CZ-160
Manufacturer:
AD
Quantity:
210
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Part Number:
ADSP-21060CZ-160
Manufacturer:
AD31
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Manufacturer:
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ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC
TRANSMIT
LINK PORT ENABLE/THREE-STATE DELAY FROM INSTRUCTION
RECEIVE
LACK (OUT)
LINK PORT INTERRUPT SETUP TIME
LDAT(3:0)
LDAT(3:0)
LACK (IN)
LDAT(3:0)
LCLK 1x
LCLK 2x
LCLK 1x
LCLK 2x
LCLK
LACK
CLKIN
CLKIN
CLKIN
CLKIN
OR
LCLK
LACK
OR
LINK PORT ENABLE OR THREE-STATE TAKES EFFECT 2 CYCLES AFTER A WRITE TO A LINK PORT CONTROL REGISTER.
THE
t
t
SLACH
t
t
ENDLK
DLCLK
DLAHC
OUT
t
t
REQUIREMENT APPLIES TO THE RISING EDGE OF LCLK ONLY FOR THE FIRST NIBBLE TRANSMITTED.
HLDCH
LCLKTWH
t
DLDCH
t
LCLKRWH
t
LCLKTWL
t
SLCK
t
SLDCL
t
IN
HLCK
t
LCLKIW
TRANSMITTED
LAST NIBBLE
Rev. F | Page 41 of 64 | March 2008
t
HLDCL
Figure 24. Link Ports—Receive
t
t
SLACH
LCLKRWL
t
TDLK
TRANSMITTED
FIRST NIBBLE
t
HLACH
t
DLALC
LCLK INACTIVE
(HIGH)
t
DLACLK