ADSP-21060CZ-160 Analog Devices Inc, ADSP-21060CZ-160 Datasheet - Page 19
![Digital Signal Processor IC](/photos/6/71/67197/qs-240-2_sml.jpg)
ADSP-21060CZ-160
Manufacturer Part Number
ADSP-21060CZ-160
Description
Digital Signal Processor IC
Manufacturer
Analog Devices Inc
Series
SHARC®r
Type
Floating Pointr
Datasheet
1.ADSP-21062KSZ-133.pdf
(64 pages)
Specifications of ADSP-21060CZ-160
Peak Reflow Compatible (260 C)
No
Supply Voltage Max
5.25V
Dsp Type
Fixed / Floating Point
Leaded Process Compatible
No
Mounting Type
Surface Mount
Package / Case
240-MQFP
Interface
Host Interface, Link Port, Serial Port
Clock Rate
40MHz
Non-volatile Memory
External
On-chip Ram
512kB
Voltage - I/o
5.00V
Voltage - Core
5.00V
Operating Temperature
-40°C ~ 100°C
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ADSP-21060CZ-160
Manufacturer:
AD
Quantity:
210
Company:
Part Number:
ADSP-21060CZ-160
Manufacturer:
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Manufacturer:
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ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC
INTERNAL POWER DISSIPATION (3.3 V)
These specifications apply to the internal power portion of V
only. For a complete discussion of the code used to measure
power dissipation, see the technical note “SHARC Power Dissi-
pation Measurements.”
Specifications are based on the operating scenarios.
To estimate power consumption for a specific application, use
the following equation where % is the amount of time your pro-
gram spends in that state:
1
2
3
Operation
Instruction Type
Instruction Fetch
Core memory Access
Internal Memory DMA
Parameter
I
I
I
I
The test program used to measure I
I
Idle denotes ADSP-2106xL state during execution of IDLE instruction.
DDINPEAK
DDINHIGH
DDINLOW
DDIDLE
measurements made using typical applications are less than specified.
DDINHIGH
%PEAK I
%IDLE I
Supply Current (Idle)
Supply Current (Internal)
is a composite average based on a range of high activity code. I
Supply Current (Internal)
Supply Current (Internal)
DDIDLE
DDINPEAK
= Power Consumption
+ %HIGH I
3
DDINPEAK
DDINHIGH
2
1
2
represents worst case processor operation and is not sustainable under normal application conditions. Actual internal power
+ %LOW I
DDINLOW
Peak Activity (I
Multifunction
Cache
2 per Cycle (DM and PM)
1 per Cycle
Test Conditions
t
t
t
t
t
t
V
CK
CK
CK
CK
CK
CK
Rev. F | Page 19 of 64 | March 2008
DD
= 30 ns, V
= 25 ns, V
= 30 ns, V
= 25 ns, V
= 30 ns, V
= 25 ns, V
= Max
+
DDINLOW
DD
DD
DD
DD
DD
DD
DD
= Max
= Max
= Max
= Max
= Max
= Max
DDINPEAK
is a composite average based on a range of low activity code.
)
High Activity (I
Multifunction
Internal Memory
1 per Cycle (DM)
1 per 2 Cycles
Max
540
600
425
475
250
275
180
DDINHIGH
)
Low Activity (I
Single Function
Internal Memory
None
1 per 2 Cycles
Units
mA
mA
mA
mA
mA
mA
mA
DDINLOW
)