ADC1210S065HN/C1:5 NXP Semiconductors, ADC1210S065HN/C1:5 Datasheet - Page 16

• Manufacturer Part Number: ADC1210S065HN/C1:5
• Description: ADC1210S065HN/HVQFN40/REEL13DP
• Manufacturer: NXP Semiconductors

Specifications of ADC1210S065HN/C1:5

• Number Of Bits: 12
• Sampling Rate (per Second): 65M
• Data Interface: Serial, SPI™
• Number Of Converters: 1
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 40-VFQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935289036518; ADC1210S065HN,518; ADC1210S065HN,518

NXP Semiconductors
ADC1210S_SER
Product data sheet
11.1.4
11.2.1 Input stage
11.2.2 Anti-kickback circuitry
11.2 Analog inputs
Selecting the output data format
The output data format can be selected via the SPI interface (offset binary, two’s
complement or gray code; see
binary or two’s complement). Offset binary is selected when DFS is LOW. When DFS is
HIGH, two’s complement is selected.
The analog input of the ADC1210S supports a differential or a single-ended input drive.
Optimal performance is achieved using differential inputs with the common-mode input
voltage (V
The full-scale analog input voltage range is configurable between 1 V (p-p) and 2 V (p-p)
via a programmable internal reference (see
The equivalent circuit of the sample and hold input stage, including Electrostatic
Discharge (ESD) protection and circuit and package parasitics, is shown in
The sample phase occurs when the internal clock (derived from the clock signal on pin
CLKP/CLKM) is HIGH. The voltage is then held on the sampling capacitors. When the
clock signal goes LOW, the stage enters the hold phase and the voltage information is
transmitted to the ADC core.
Anti-kickback circuitry (R-C filter in
charge injection generated by the sampling capacitance.
The RC filter is also used to filter noise from the signal before it reaches the sampling
stage. The value of the capacitor should be chosen to maximize noise attenuation without
degrading the settling time excessively.
Fig 16. Input sampling circuit
I(cm)
INM
INP
) on pins INP and INM set to 0.5V
All information provided in this document is subject to legal disclaimers.
8
7
Rev. 2 — 23 December 2010
Package
Table
Single 12-bit ADC; CMOS or LVDS DDR digital outputs
Figure
23) or by using pin DFS in Pin control mode (offset
ESD
17) is needed to counteract the effects of a
Section 11.3
Parasitics
DDA
.
ADC1210S series
R on = 15 Ω
R on = 15 Ω
Internal
Internal
Switch
Switch
clock
clock
and
Table
Sampling
Sampling
capacitor
capacitor
4 pF
4 pF
22).
005aaa043
© NXP B.V. 2010. All rights reserved.
Figure
16.
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