ADC1112D125HN/C1:5 NXP Semiconductors, ADC1112D125HN/C1:5 Datasheet - Page 23

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ADC1112D125HN/C1:5

Manufacturer Part Number
ADC1112D125HN/C1:5
Description
ADC1112D125HN/HVQFN64/REEL13DP
Manufacturer
NXP Semiconductors
Datasheet

Specifications of ADC1112D125HN/C1:5

Number Of Bits
11
Sampling Rate (per Second)
125M
Data Interface
Serial, SPI™
Number Of Converters
2
Voltage Supply Source
Single Supply
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
64-VFQFN Exposed Pad
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
NXP Semiconductors
ADC1112D125
Product data sheet
11.4.2 Equivalent input circuit
The equivalent circuit of the input clock buffer is shown in
voltage of the differential input stage is set via internal 5 kΩ resistors.
Fig 27. Differential clock input
Fig 28. Equivalent input circuit
a. Sine clock input
c. LVPECL clock input
V
CLKM
CLKP
cm(clk)
clock input
Sine
= common-mode voltage of the differential input stage.
All information provided in this document is subject to legal disclaimers.
Package
Rev. 2 — 3 March 2011
005aaa173
CLKM
CLKP
ESD
Dual 11-bit ADC: CMOS or LVDS DDR digital outputs
clock input
LVPECL
Parasitics
005aaa172
CLKM
CLKP
clock input
b. Sine clock input (with transformer)
Sine
SE_SEL
Figure
5 kΩ
ADC1112D125
V
cm(clk)
28. The common-mode
SE_SEL
5 kΩ
© NXP B.V. 2011. All rights reserved.
005aaa056
005aaa054
CLKM
CLKP
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