AD9980KSTZ-80 Analog Devices Inc, AD9980KSTZ-80 Datasheet - Page 37

• Manufacturer Part Number: AD9980KSTZ-80
• Description: IC,Data Acquisition Signal Conditioner,3-CHANNEL,8-BIT,CMOS,QFP,80PIN,PLASTIC
• Manufacturer: Analog Devices Inc

Specifications of AD9980KSTZ-80

• Applications: Video
• Interface: Analog
• Voltage - Supply: 3.13 V ~ 3.47 V
• Package / Case: 80-LQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AD9980/PCBZ - KIT EVALUATION AD9980
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

0x25
Table 70. Detected Vsync0 Polarity Results
Detect
0
1
0x25
Table 71. Detected Vsync1 Polarity Results
Detect
0
1
0x25
Table 72. Detected Coast Polarity Results
Detect
0
1
0x25
Table 73. Detected Clamp Polarity Results
Detect
0
1
0x25
A second output from the Hsync filter, this status bit tells
whether extraneous pulses are present on the incoming sync
signal. Often extraneous pulses are used for copy protection, so
this status bit can be used for this purpose.
Table 74. Equalization Pulse Detect Bit
HSYNC COUNT
0x26
0x27
Detect
0
1
5
Indicates the polarity of Vsync0 input.
4
Indicates the polarity of Vsync1 input.
3
Indicates the polarity of the external Coast signal.
2
Indicates the polarity of the clamp signal.
1
7:0
The 8 MSBs of the 12-bit counter that reports the
number of Hsyncs/Vsync on the active input. This is
useful for determining the mode and is an aid in
setting the PLL divide ratio.
7:4
The 4 LSBs of the 12-bit counter that reports the
number of Hsyncs/Vsync on the active input.
Vsync0 Polarity
Vsync1 Polarity
Coast Polarity
Clamp Polarity
Extraneous Pulses Detection
Hsyncs/Vsync MSB
Hsyncs/Vsync LSBs
Result
Vsync polarity is negative
Vsync polarity is positive
Result
Vsync polarity is negative
Vsync polarity is positive
Result
Coast polarity is negative
Coast polarity is positive
Result
Clamp polarity is negative
Clamp polarity is positive
Result
No equalization pulses detected during
active Hsync
Equalization pulses detected during
active Hsync
Rev. 0 | Page 37 of 44
Test Registers
0x28
0x29
0x2A
0x2B
0x2C
0x2C
Table 75. Auto-Offset Hold
0x2C
0x2D
0x2E
Select
0
1
7:0
Must be written to 0xBF for proper operation.
7:0
Must be written to 0x00 for proper operation.
7:0
Read only bits for future use.
7:0
Read only bits for future use.
7:5
Must be written to 000 for proper operation.
4
A bit for controlling whether the auto-offset function
runs continuously or runs once and holds the result.
Continuous updates are recommended because it
allows the AD9980 to compensate for drift-over time,
temperature, etc. If one-time updates are preferred,
these should be performed every time the part is
powered up and when there is a mode change. To do a
one-time update, first auto-offset must be enabled
(Register 0x1B, Bit 5). Next, this bit (auto-offset hold)
must first be set to 0 to let the auto-offset function
operate and settle to a final value. Auto-offset hold
should then be set to 1 to hold the offset values that
the auto circuitry calculates. The AD9980’s auto-offset
circuit’s maximum settle time is 10 updates. For
example, if the update frequency is set to once every
64 Hsyncs, then the maximum settling time would be
640 Hsyncs (10 × 64 Hsyncs).
3:0
7:0
Read/write bits for future use. Must be written to
0xE8 for proper operation.
7:0
Read/write bits for future use. Must be written to
0xE0 for proper operation.
Result
Allows auto-offset to update continuously
Disables auto-offset updates and holds the
current auto-offset values
Test Register 1
Test Register 2
Test Register 3
Test Register 4
Auto-Offset Hold
Must be written to 0x0 for proper operation.
Test Register 5
Test Register 6
AD9980