AD9980KSTZ-80 Analog Devices Inc, AD9980KSTZ-80 Datasheet - Page 23

• Manufacturer Part Number: AD9980KSTZ-80
• Description: IC,Data Acquisition Signal Conditioner,3-CHANNEL,8-BIT,CMOS,QFP,80PIN,PLASTIC
• Manufacturer: Analog Devices Inc

Specifications of AD9980KSTZ-80

• Applications: Video
• Interface: Analog
• Voltage - Supply: 3.13 V ~ 3.47 V
• Package / Case: 80-LQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AD9980/PCBZ - KIT EVALUATION AD9980
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Hexadecimal
Address
0x12
0x13
0x14
0x15
0x16
0x17
0x18
Read and
Write or
Read Only
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bits
7
6
5
4
3
7:0
7
6
5
4
3
2
1
7:0
7:0
7:0
7
6
0*** ****
*0** ****
**0* ****
***1 ****
**** 1***
0*** ****
*0** ****
**0* ****
***1 ****
**** 1***
**** *0**
**** **0*
0*** ****
*0** ****
Default
Value
0010 0000
0000 1010
0000 0000
0000 0000
Register
Name
Hsync Control
Hsync
Duration
Vsync Control
Vsync Duration
Precoast
Postcoast
Coast and
Clamp Control
Rev. 0 | Page 23 of 44
Description
Active Hsync Override.
0 = The chip determines the active Hsync source.
1 = The active Hsync Source is set by 0x12, Bit 6.
Selects the source of the Hsync for PLL and sync processing. This
bit is used only if 0x12, Bit 7 is set to 1 or if both syncs are active.
0 = Hsync is from Hsync input pin.
1 = Hsync is from SOG.
Hsync Polarity Override.
0 = The chip selects the Hsync input polarity.
1 = The polarity of the input Hsync is controlled by 0x12, Bit 4.
This applies to both Hsync0 and Hsync1.
Hsync input polarity: this bit is used only if 0x12, Bit 5 is set to 1.
0 = Active low input Hsync.
1 = Active high input Hsync.
Sets the polarity of the Hsync output signal.
0 = Active low Hsync output.
1 = Active high Hsync output.
Sets the number of pixel clocks that Hsync out is active.
Active Vsync Override.
0 = The chip determines the active Vsync source.
1 = The active Vsync source is set by 0x14, Bit 6.
Selects the source of Vsync for the sync processing. This bit is used
only if 0x14, Bit 7 is set to 1.
0 = Vsync is from the Vsync input pin.
1 = Vsync is from the sync separator.
Vsync Polarity Override.
0 = The chip selects the input Vsync polarity.
1 = The polarity of the input Vsync is set by 0x14, Bit 4.
This applies to both Vsync0 and Vsync1.
Vsync input polarity: this bit is used only if 0x14, Bit 5 is set to 1.
0 = Active low input Vsync.
1 = Active high input Vsync.
Sets the polarity of the output Vsync signal.
0 = Active low output Vsync.
1 = Active high output Vsync.
0 = The Vsync filter is disabled.
1 = The Vsync filter is enabled.
This needs to be enabled when using the Hsync to Vsync counter.
Enables the Vsync duration block. This is designed to be used with
the Vsync filter.
0 = Vsync output duration is unchanged.
1 = Vsync output duration is set by Register 0x15.
Sets the number of Hsyncs that Vsync out is active. This is only
used if 0x14, Bit 1 is set to 1.
The number of Hsync periods to Coast prior to Vsync.
The number of Hsync periods to Coast after Vsync.
Coast Source.
Selects the source of the Coast signal.
0 = Using internal Coast generated from Vsync.
1 = Using external Coast signal from external COAST pin.
Coast Polarity Override.
0 = The chip selects the external Coast polarity.
1 = The polarity of the external Coast signal is set by 0x18, Bit 5.
AD9980