AD9980KSTZ-80 Analog Devices Inc, AD9980KSTZ-80 Datasheet - Page 35

• Manufacturer Part Number: AD9980KSTZ-80
• Description: IC,Data Acquisition Signal Conditioner,3-CHANNEL,8-BIT,CMOS,QFP,80PIN,PLASTIC
• Manufacturer: Analog Devices Inc

Specifications of AD9980KSTZ-80

• Applications: Video
• Interface: Analog
• Voltage - Supply: 3.13 V ~ 3.47 V
• Package / Case: 80-LQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AD9980/PCBZ - KIT EVALUATION AD9980
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

0x1F
Table 52. Output Drive Strength
Output
Drive
00
01
10
11
0x1F
Table 53. Output Clock Invert
Select
0
1
0x20
Table 54. Output Clock Select
Select
00
01
10
11
0x20
This bit puts all outputs (except SOGOUT) in a high impedance
state. The power-up default setting is 0.
Table 55. Output High Impedance
Select
0
1
0x20
Table 56. SOGOUT High Impedance
Select
0
1
Result
Normal outputs
All outputs (except SOGOUT) in high impedance mode
2:1
These two bits select the drive strength for all high-
speed digital outputs (except VSOUT, A0, and the O/E
field). Higher drive strength results in faster rise/fall
times and in general makes it easier to capture data.
Lower drive strength results in slower rise/fall times
and helps reduce EMI and digitally generated power
supply noise. The power-up default setting is 10.
0
This bit allows inversion of the output clock. The
power-up default setting is 0.
7:6
These bits allow selection of optional output clocks
such as a fixed 40 MHz clock, a 2× clock, a 90° phase-
shifted clock or the normal pixel clock. The power-up
default setting is 00.
5
4
This bit allows the SOGOUT pin to be placed in high
impedance mode. The power-up default setting is 0.
Result
Normal SOG output
SOGOUT pin is in high impedance mode
Result
Pixel clock
90° phase-shifted pixel clock
2× pixel clock
40 MHz internal clock
Result
Low output drive strength
Medium low output drive strength
Medium high output drive strength
High output drive strength
Result
Noninverted pixel clock
Inverted pixel clock
Output Drive Strength
Output Clock Invert
Output Clock Select
Output High Impedance
SOG High Impedance
Rev. 0 | Page 35 of 44
0x20
Table 57. Field Output Polarity
Select
0
1
SYNC PROCESSING
0x20
Table 58. PLL Sync Filter Enable
Select
0
1
0x20
Table 59. SP Filter Enable
Select
0
1
0x20
0x21
0x22
0x23
This 8-bit register sets the window of time for the regenerated
Hsync leading edge (in 25 ns steps) when sync pulses are
allowed to pass through. Therefore with the default value of 10,
the window width is ±250 ns. The goal is to set the window
width so that extraneous pulses are rejected. (see the Sync
Processing section). As in the sync separator threshold, the
25 ns multiplier value is somewhat variable. The maximum
variability over all operating conditions is ±20% (20 ns to
30 ns).
3
This bit sets the polarity of the field output bit. The
power-up default setting is 1.
2
This bit selects which signal the PLL uses. It can select
between either raw Hsync or SOG or filtered versions.
The filtering of the Hsync and SOG can eliminate
nearly all extraneous transitions which have tradi-
tionally caused PLL disruption. The power-up default
setting is 0.
1
This bit selects whether the sync processor uses a raw
sync or a regenerated sync for the following functions:
Coast, H/V count, field detection and Vsync duration
counts. Using the regenerated sync is recommended.
0
7:0
7:0
7:0
Result
Active low = even field; active high = odd field
Active low = odd field; active high = even field
Result
PLL uses raw Hsync or SOG inputs
PLL uses filtered Hsync or SOG inputs
Result
Sync processing uses raw Hsync or SOG
Sync processing uses the internally regenerated
Hsync
Field Output Polarity
PLL Sync Filter
Sync Processing Input Source
Must be set to 1 for proper operation
Must be set to default
Must be set to default
Sync Filter Window Width
AD9980