AD9627BCPZ-105 Analog Devices Inc, AD9627BCPZ-105 Datasheet - Page 12

• Manufacturer Part Number: AD9627BCPZ-105
• Description: IC,A/D CONVERTER,DUAL,12-BIT,LLCC,64PIN
• Manufacturer: Analog Devices Inc

Specifications of AD9627BCPZ-105

• Number Of Bits: 12
• Sampling Rate (per Second): 105M
• Data Interface: Serial, SPI™
• Number Of Converters: 2
• Power Dissipation (max): 650mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LFCSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AD9627-150EBZ - BOARD EVAL FOR AD9627-150AD9627-125EBZ - IC A/D 12BIT 125MSPS DL EVAL BRD
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9627
SWITCHING SPECIFICATIONS—AD9627-125/AD9627-150
AVDD = 1.8 V, DVDD = 1.8 V, DRVDD = 3.3 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, and
DCS enabled, unless otherwise noted.
Table 7.
Parameter
CLOCK INPUT PARAMETERS
DATA OUTPUT PARAMETERS (DATA, FD)
OUT-OF-RANGE RECOVERY TIME
1
2
3
Conversion rate is the clock rate after the divider.
Output propagation delay is measured from CLK 50% transition to DATA 50% transition, with 5 pF load.
Wake-up time is dependent on the value of the decoupling capacitors.
Input Clock Rate
Conversion Rate
CLK Period—Divide-by-1 Mode (t
CLK Pulse Width High
CMOS Mode—DRVDD = 3.3 V
CMOS Mode—DRVDD = 1.8 V
LVDS Mode—DRVDD = 1.8 V
CMOS Mode Pipeline Delay (Latency)
LVDS Mode Pipeline Delay (Latency)
Aperture Delay (t
Aperture Uncertainty (Jitter, t
Wake-Up Time
Data Propagation Delay (t
DCO Propagation Delay (t
DCS Enabled
DCS Disabled
Divide-by-1 Mode, DCS Enabled
Divide-by-1 Mode, DCS Disabled
Divide-by-2 Mode, DCS Enabled
Divide-by-3-Through-8 Mode,
Data Propagation Delay (t
DCO Propagation Delay (t
Setup Time (t
Hold Time (t
Setup Time (t
Hold Time (t
Data Propagation Delay (t
DCO Propagation Delay (t
Channel A/Channel B
DCS Enabled
3
H
H
1
S
)
S
)
1
)
)
A
)
DCO
PD
PD
DCO
PD
DCO
J
)
)
)
)
2
2
)
2
)
)
CLK
)
Temperature
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Rev. B | Page 12 of 76
Min
20
10
8
2.4
3.6
1.6
0.8
2.2
3.8
2.4
4.0
2.0
5.2
AD9627-125
Typ
4
4
4.5
5.0
4.5
3.5
5.2
5.6
4.4
3.6
4.8
7.3
12
12/12.5
1.0
0.1
350
3
Max
625
125
125
5.6
4.4
6.4
6.8
6.9
7.3
6.3
9.0
Min
20
10
6.66
2.0
3.0
1.6
0.8
2.2
3.8
2.4
4.0
2.0
5.2
AD9627-150
Typ
3.33
3.33
4.5
5.0
3.83
2.83
5.2
5.6
3.73
2.93
4.8
7.3
12
12/12.5
1.0
0.1
350
3
Max
625
150
150
4.66
3.66
6.4
6.8
6.9
7.3
6.3
9.0
Unit
MHz
MSPS
MSPS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Cycles
Cycles
ns
ps rms
μs
Cycles