AD9627BCPZ-105 Analog Devices Inc, AD9627BCPZ-105 Datasheet
AD9627BCPZ-105
Specifications of AD9627BCPZ-105
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AD9627BCPZ-105 Summary of contents
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FEATURES SNR = 69.4 dBc (70.4 dBFS MHz @ 125 MSPS SFDR = 85 dBc to 70 MHz @ 125 MSPS Low power: 750 mW @ 125 MSPS SNR = 69.2 dBc (70.2 dBFS MHz @ ...
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AD9627 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 Functional Block Diagram .............................................................. 1 Product Highlights ........................................................................... 1 Revision History ............................................................................... 3 General Description ......................................................................... 4 Specifications ..................................................................................... 5 ADC DC Specifications—AD9627-80/AD9627-105 .................. 5 ADC DC Specifications—AD9627-125/AD9627-150 ................ 6 ...
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... REVISION HISTORY 5/10—Rev Rev. B Deleted CP-64-3 Package .................................................. Universal Added CP-64-6 Package .................................................... Universal Changed AD9627BCPZ-80 to AD9267-80 and AD9627BCPZ-105 to AD9627-105 Throughout .......................... 5 Changed AD9627BCPZ-125 to AD9267-125 and AD9627BCPZ-150 to AD9627-150 Throughout .......................... 6 Changes to Figure 6 ......................................................................... 16 Changes to Figure 7 ......................................................................... 18 Updated Outline Dimensions ........................................................ 74 Changes to Ordering Guide ........................................................... 74 6/09—Rev Rev. A Changes to Table 6 ...
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AD9627 GENERAL DESCRIPTION The AD9627 is a dual, 12-bit, 80 MSPS/105 MSPS/125 MSPS/ 150 MSPS analog-to-digital converter (ADC). The AD9627 is designed to support communications applications where low cost, small size, and versatility are desired. The dual ADC core features ...
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SPECIFICATIONS ADC DC SPECIFICATIONS—AD9627-80/AD9627-105 AVDD = 1.8 V, DVDD = 1.8 V, DRVDD = 3.3 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, DCS enabled, fast detect output pins disabled, and signal monitor disabled, ...
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AD9627 ADC DC SPECIFICATIONS—AD9627-125/AD9627-150 AVDD = 1.8 V, DVDD = 1.8 V, DRVDD = 3.3 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, DCS enabled, fast detect output pins disabled, and signal monitor disabled, ...
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ADC AC SPECIFICATIONS—AD9627-80/AD9627-105 AVDD = 1.8 V, DVDD = 1.8 V, DRVDD = 3.3 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, DCS enabled, fast detect output pins disabled, and signal monitor disabled, unless ...
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AD9627 ADC AC SPECIFICATIONS—AD9627-125/AD9627-150 AVDD = 1.8 V, DVDD = 1.8 V, DRVDD = 3.3 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, DCS enabled, fast detect output pins disabled, and signal monitor disabled, ...
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DIGITAL SPECIFICATIONS AVDD = 1.8 V, DVDD = 1.8 V, DRVDD = 3.3 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, and DCS enabled, unless otherwise noted. Table 5. Parameter DIFFERENTIAL CLOCK INPUTS (CLK+, ...
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AD9627 Parameter Input Resistance Input Capacitance DIGITAL OUTPUTS CMOS Mode—DRVDD = 3.3 V High Level Output Voltage μ 0 Low Level Output Voltage μA ...
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SWITCHING SPECIFICATIONS—AD9627-80/AD9627-105 AVDD = 1.8 V, DVDD = 1.8 V, DRVDD = 3.3 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, and DCS enabled, unless otherwise noted. Table 6. Parameter CLOCK INPUT PARAMETERS Input ...
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AD9627 SWITCHING SPECIFICATIONS—AD9627-125/AD9627-150 AVDD = 1.8 V, DVDD = 1.8 V, DRVDD = 3.3 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, and DCS enabled, unless otherwise noted. Table 7. Parameter CLOCK INPUT PARAMETERS ...
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TIMING SPECIFICATIONS Table 8. Parameter Conditions SYNC TIMING REQUIREMENTS t SYNC to rising edge of CLK setup time SSYNC t SYNC to rising edge of CLK hold time HSYNC SPI TIMING REQUIREMENTS t Setup time between the data and the ...
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AD9627 CLK+ CLK– CH A/CH B DATA A N – A/CH B FAST A DETECT N – 7 DCO+ DCO– Figure 3. LVDS Mode Data and Fast Detect Output Timing (Fast Detect Mode Select Bits = 001 Through ...
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ABSOLUTE MAXIMUM RATINGS Table 9. Parameter ELECTRICAL AVDD, DVDD to AGND DRVDD to DRGND AGND to DRGND AVDD to DRVDD VIN+A/VIN+B, VIN−A/VIN−B to AGND CLK+, CLK− to AGND SYNC to AGND VREF to AGND SENSE to AGND CML to AGND ...
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AD9627 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS DRVDD D11B (MSB) D0A (LSB) Table 11. Pin Function Descriptions (Parallel CMOS Mode) Pin No. Mnemonic Type ADC Power Supplies 20, 64 DRGND Ground 1, 21 DRVDD Supply 24, 57 DVDD Supply 36, 45, ...
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Pin No. Mnemonic Type Digital Input 52 SYNC Input Digital Outputs 14 D0A (LSB) Output 15 D1A Output 16 D2A Output 17 D3A Output 18 D4A Output 19 D5A Output 22 D6A Output 23 D7A Output 25 D8A Output 26 ...
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AD9627 DRVDD D0– (LSB) D0+ (LSB) DCO– DCO+ Table 12. Pin Function Descriptions (Interleaved Parallel LVDS Mode) Pin No. Mnemonic Type ADC Power Supplies 20, 64 DRGND Ground 1, 21 DRVDD Supply 24, 57 DVDD Supply 36, 45, 46 AVDD ...
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Pin No. Mnemonic Type Digital Outputs 5 D0+ (LSB) Output 4 D0− (LSB) Output 7 D1+ Output 6 D1− Output 9 D2+ Output 8 D2− Output 13 D3+ Output 12 D3− Output 15 D4+ Output 14 D4− Output 17 D5+ ...
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AD9627 EQUIVALENT CIRCUITS VIN Figure 8. Equivalent Analog Input Circuit AVDD 1.2V 10kΩ 10kΩ CLK+ Figure 9. Equivalent Clock Input Circuit DRVDD DRGND Figure 10. Digital Output DRVDD DRVDD 26kΩ 1kΩ SDIO/DCS Figure 11. Equivalent SDIO/DCS or SMI SDFS Circuit ...
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TYPICAL PERFORMANCE CHARACTERISTICS AVDD = 1.8 V, DVDD = 1.8 V, DRVDD = 3.3 V, sample rate = 150 MSPS, DCS enabled, 1.0 V internal reference p-p differential input, VIN = −1.0 dBFS, and 64k sample ...
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AD9627 0 150MSPS 440MHz @ –1dBFS SNR = 65.7dBc (66.7dBFS) –20 ENOB = 10.4 BITS SFDR = 70.0dBc –40 SECOND –60 HARMONIC THIRD –80 HARMONIC –100 –120 FREQUENCY (MHz) Figure 22. AD9627-150 Single-Tone FFT with ...
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SFDR (dBFS) 100 80 SNR (dBFS SFDR (dBc) 85dB REFERENCE LINE 20 SNR (dBc) 0 –90 –80 –70 –60 –50 –40 INPUT AMPLITUDE (dBFS) Figure 28. AD9627-150 Single-Tone SNR/SFDR vs. Input Amplitude (A with f = 2.4 ...
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AD9627 0 –20 SFDR (dBc) –40 IMD3 (dBc) –60 –80 SFDR (dBFS) –100 IMD3 (dBFS) –120 –90 –78 –66 –54 –42 INPUT AMPLITUDE (dBFS) Figure 34. AD9627-150 Two-Tone SFDR/IMD3 vs. Input Amplitude (A with f = 169.1 MHz ...
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N – – – OUTPUT CODE Figure 40. AD9627 Grounded Input Histogram 0.4 0.3 0.2 0.1 0 –0.1 –0.2 –0.3 –0.4 0 512 1024 ...
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AD9627 THEORY OF OPERATION The AD9627 dual ADC design can be used for diversity reception of signals, where the ADCs are operating identically on the same carrier but from two separate antennae. The ADCs can also be operated with independent ...
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The output common-mode voltage of the AD8138 is easily set with the CML pin of the AD9627 (see Figure 46), and the driver can be configured in a Sallen-Key filter topology to provide band limiting of the input signal. 499Ω ...
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AD9627 VOLTAGE REFERENCE A stable and accurate voltage reference is built into the AD9627. The input range can be adjusted by varying the reference voltage applied to the AD9627, using either the internal reference or an externally applied reference voltage. ...
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External Reference Operation The use of an external reference may be necessary to enhance the gain accuracy of the ADC or improve thermal drift charac- teristics. Figure 54 shows the typical drift characteristics of the internal reference in 1.0 V ...
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AD9627 In some applications, it may be acceptable to drive the sample clock inputs with a single-ended CMOS signal. In such applica- tions, the CLK+ pin should be driven directly from a CMOS gate, and the CLK− pin should be ...
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POWER DISSIPATION AND STANDBY MODE As shown in Figure 63 through Figure 66, the power dissipated by the AD9627 is proportional to its sample rate. In CMOS output mode, the digital power dissipation is determined primarily by the strength of ...
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AD9627 DIGITAL OUTPUTS The AD9627 output drivers can be configured to interface with 1 3.3 V CMOS logic families by matching DRVDD to the digital supply of the interfaced logic. The AD9627 can also be configured for LVDS ...
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ADC OVERRANGE AND GAIN CONTROL In receiver applications desirable to have a mechanism to reliably determine when the converter is about to be clipped. The standard overflow indicator provides after-the-fact infor- mation on the state of the analog ...
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AD9627 When the fast detect mode select bits are set to 0b001, 0b010, or 0b011, a subset of the fast detect output pins is available. In these modes, the fast detect output pins have a latency of six clock cycles. ...
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Increment Gain (IG) and Decrement Gain (DG) The increment gain and decrement gain indicators are intended to be used together to provide information to enable external gain control. The decrement gain indicator works in conjunction with the coarse upper threshold ...
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AD9627 SIGNAL MONITOR The signal monitor block provides additional information about the signal being digitized by the ADC. The signal monitor computes the rms input magnitude, the peak magnitude, and/or the number of samples by which the magnitude exceeds a ...
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Figure 69 illustrates the rms magnitude monitoring logic. FROM MEMORY MAP SIGNAL MONITOR DOWN IS COUNT = 1? PERIOD REGISTER COUNTER LOAD FROM CLEAR LOAD INPUT SIGNAL MONITOR PORTS ACCUMULATOR REGISTER (SMR) Figure 69. ADC Input RMS Magnitude Monitoring Block ...
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AD9627 DC Correction Bandwidth The dc correction circuit is a high-pass filter with a programmable bandwidth (ranging between 0.15 Hz and 1.2 kHz at 125 MSPS). The bandwidth is controlled by writing the 4-bit dc correction register located at Register ...
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BUILT-IN SELF-TEST (BIST) AND OUTPUT TEST The AD9627 includes built-in test features designed to enable verification of the integrity of each channel as well as facilitate board level debugging. A BIST (built-in self-test) feature is included that verifies the integrity ...
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AD9627 CHANNEL/CHIP SYNCHRONIZATION The AD9627 has a SYNC input that offers the user flexible synchronization options for synchronizing the internal blocks. The clock divider sync feature is useful for guaranteeing synchro- nized sample clocks across multiple ADCs. The signal monitor ...
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SERIAL PORT INTERFACE (SPI) The AD9627 serial port interface (SPI) allows the user to configure the converter for specific functions or operations through a structured register space provided inside the ADC. The SPI gives the user added flexibility and customization, ...
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AD9627 CONFIGURATION WITHOUT THE SPI In applications that do not interface to the SPI control registers, the SDIO/DCS pin, the SCLK/DFS pin, the SMI SDO/OEB pin, and the SMI SCLK/PDWN pin serve as standalone CMOS- compatible control pins. When the ...
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MEMORY MAP READING THE MEMORY MAP REGISTER TABLE Each row in the memory map register table has eight bit locations. The memory map is roughly divided into four sections: the chip configuration registers (Address 0x00 to Address 0x02); the channel ...
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AD9627 MEMORY MAP REGISTER TABLE All address and bit locations that are not included in Table 25 are not currently supported for this device. Table 25. Memory Map Registers Addr Register Bit 7 (Hex) Name (MSB) Bit 6 Chip Configuration ...
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Addr Register Bit 7 Bit 6 (Hex) Name (MSB) 0x0E BIST Enable Open Open (Local) 0x10 Offset Adjust Open Open (Local) 0x14 Output Mode Drive Output type strength 0 = CMOS 3 LVDS CMOS ...
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AD9627 Addr Register Bit 7 Bit 6 (Hex) Name (MSB) 0x109 Fine Lower Open Open Threshold Register 1 (Local) 0x10A Increase Gain Dwell Time Register 0 (Local) 0x10B Increase Gain Dwell Time Register 1 (Local) 0x10C Signal Monitor Open DC ...
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Addr Register Bit 7 Bit 6 (Hex) Name (MSB) 0x117 Signal Monitor Result Channel A Register 1 (Global) 0x118 Signal Monitor Open Open Result Channel A Register 2 (Global) 0x119 Signal Monitor Result Channel B Register 0 (Global) 0x11A Signal ...
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AD9627 Increase Gain Dwell Time (Register 0x10A and Register 0x10B) Register 0x10A, Bits[7:0]—Increase Gain Dwell Time[7:0] Register 0x10B, Bits[7:0]—Increase Gain Dwell Time[15:8] These registers are programmed with the dwell time in ADC clock cycles for which the signal must be ...
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Signal Monitor Period (Register 0x113 to Register 0x115) Register 0x113, Bits[7:0]—Signal Monitor Period[7:0] Register 0x114, Bits[7:0]—Signal Monitor Period[15:8] Register 0x115, Bits[7:0]—Signal Monitor Period[23:16] This 24-bit value sets the number of clock cycles over which the signal monitor performs its operation. ...
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AD9627 APPLICATIONS INFORMATION DESIGN GUIDELINES Before starting design and layout of the AD9627 as a system recommended that the designer become familiar with these guidelines, which discuss the special circuit connections and layout requirements needed for certain pins. ...
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EVALUATION BOARD The AD9627 evaluation board provides all of the support circuitry required to operate the ADC in its various modes and configura- tions. The converter can be driven differentially through a double balun configuration (default) or optionally through the ...
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AD9627 DEFAULT OPERATION AND JUMPER SELECTION SETTINGS The following is a list of the default and optional settings or modes allowed on the AD9627 evaluation board. POWER Connect the switching power supply that is provided in the evaluation kit between ...
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ALTERNATIVE ANALOG INPUT DRIVE CONFIGURATION This section provides a brief description of the alternative analog input drive configuration using the AD8352. When using this particular drive option, some additional components need to be populated. For more details on the AD8352 ...
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AD9627 SCHEMATICS M OH 10K R41 100 R127 4.12K R126 DNP R36 24 24.9 R29 R35 F Figure 75. Evaluation Board Schematic, Channel A Analog Inputs Rev Page 06571-075 ...
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M OH 10K R53 D AMPVD M OH 100 R129 4.12K R128 DNP R68 M OH 24.9 OHM 24.9 R134 R135 F Figure 76. Evaluation Board Schematic, Channel B Analog Inputs Rev Page 06571-076 M ...
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AD9627 M OH 10K M OH 10K R85 R82 M OH 24.9 R83 57.6 R30 2 Figure 77. Evaluation Board Schematic, DUT Clock Input Rev Page 06571-077 TP2 ...
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OHM 100 R75 OHM 100 VS_OUT67_ 50 2 VS_OUT67_ 51 V VS_OUT01_DI 52 OUT1B 53 OUT1 54 VS_OUT01_DRV 55 OUT0B 56 OUT0 57 VS_REF 4.12K 58 RSET_CLOCK R12 59 GND_REF 60 VS_PRESCALER 61 2 VS_PLL_ ...
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AD9627 TP1 AC Figure 79. Evaluation Board Schematic, Optional AD9516 Loop Filter/VCO and SYNC Input 2 RES040 M OH 10K R105 2 RES040 M OH 10K R103 2 RES040 M OH 10K R102 2 RES040 M OH 10K 2 RES040 ...
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DVDD 8 RPAK FD0A 1 16 FD1A 2 15 FD2A 3 14 FD3A PWR_SD PWR_SCL PWR_SDFS RES040 R112 17 D3A 18 ...
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AD9627 M OH 10K R118 2 RES040 VAL R130 2 RES040 M OH 10K R140 Figure 81. Evaluation Board Schematic, Digital Output Interface Rev Page 06571-081 M OH 100 R77 ...
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Figure 82. Evaluation Board Schematic, SPI Circuitry Rev Page AD9627 06571-082 RES0402 OHM 10K R65 ...
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AD9627 2 M KOH 140 R13 GND 4 1 RES0603 M OH 261 A C R16 CR7 SJ35 1 S2A_REC T Figure 83. Evaluation Board Schematic, Power Supply Rev Page 06571-083 M KOH 78.7 R14 ...
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SJ37 SJ36 Figure 84. Evaluation Board Schematic, Power Supply (Continued) M KOH 140 M KOH 78 Rev Page AD9627 ...
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AD9627 EVALUATION BOARD LAYOUTS Figure 85. Evaluation Board Layout, Primary Side Rev Page ...
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Figure 86. Evaluation Board Layout, Ground Plane Rev Page AD9627 ...
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AD9627 Figure 87. Evaluation Board Layout, Power Plane Rev Page ...
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Figure 88. Evaluation Board Layout, Power Plane Rev Page AD9627 ...
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AD9627 Figure 89. Evaluation Board Layout, Ground Plane Rev Page ...
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Figure 90. Evaluation Board Layout, Secondary Side (Mirrored Image) Rev Page AD9627 ...
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AD9627 Figure 91. Evaluation Board Layout, Silkscreen, Primary Side Rev Page ...
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Figure 92. Evaluation Board Layout, Silkscreen, Secondary Side Rev Page AD9627 ...
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AD9627 BILL OF MATERIALS Table 26. Evaluation Board Bill of Materials (BOM) Reference Item Qty Designator Description 1 1 AD9627CE_REVB PCB C3, C6, C7, 0.1 μ ceramic C13, C14, C17, C18, capacitor, SMT 0402 ...
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... SOT223-HS Analog Devices SOT223-HS Analog Devices OSC-CTS-CB3 Valpey Fisher LFCSP16-3X3-PAD Analog Devices Rev Page AD9627 Mfg. Part Number NRC06F2610TRF NRC06F1003TRF NRC04F1002TRF NRC06F1001TRF NRC04J330TRF 742C163220JPTR 742C083220JPTR NCR04F2000TRF 142-0701-201 NRC10ZOTRF MABA-007159-000000 AD9627BCPZ AD9516-4BCPZ NC7WZ04P6X_NL NC7WZ07P6X_NL NC7WZ16P6X_NL 74VCX16244MTDX_NL ADP3334ACPZ ADP3339AKCZ-1.8 ADP3339AKCZ-5.0 ADP3339AKCZ-3.3 VFAC3-BHL AD8352ACPZ ...
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AD9627 OUTLINE DIMENSIONS PIN 1 INDICATOR TOP VIEW 12° MAX 1.00 0.85 0.80 SEATING PLANE ORDERING GUIDE 1 Model Temperature Range AD9627ABCPZ-150 −40°C to +85°C AD9627ABCPZ-125 −40°C to +85°C AD9627ABCPZ-105 −40°C to +85°C AD9627ABCPZ-80 −40°C to +85°C AD9627-150EBZ AD9627-125EBZ 1 ...
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NOTES Rev Page AD9627 ...
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AD9627 NOTES ©2007–2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06571-0-5/10(B) Rev Page ...