AD9600BCPZ-105 Analog Devices Inc, AD9600BCPZ-105 Datasheet - Page 39

• Manufacturer Part Number: AD9600BCPZ-105
• Description: IC,A/D CONVERTER,DUAL,10-BIT,CMOS,LLCC,64PIN
• Manufacturer: Analog Devices Inc

Specifications of AD9600BCPZ-105

• Number Of Bits: 10
• Sampling Rate (per Second): 105M
• Data Interface: Serial, SPI™
• Number Of Converters: 2
• Power Dissipation (max): 650mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LFCSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

CONFIGURATION WITHOUT THE SPI
In applications that do not interface to the SPI control registers,
the SDIO/DCS pin, the SCLK/DFS pin, the SMI SDO/OEB pin,
and the SMI SCLK/PDWN pin serve as standalone CMOS-
compatible control pins. When the device is powered up, it is
assumed that the user intends to use the pins as static control
lines for the duty cycle stabilizer, output data format, output
enable, and power-down feature control. In this mode, the CSB
chip select should be connected to AVDD, which disables the
serial port interface.
Table 20. Mode Selection
Pin
SDIO/DCS
SCLK/DFS
SMI SDO/OEB
SMI SCLK/PDWN
SCLK
SDIO
CSB
DON’T CARE
DON’T CARE
t
S
External
Voltage
AVDD (default)
AGND
AVDD
AGND (default)
AVDD
AGND (default)
AVDD
AGND (default)
R/W
t
DS
W1
W0
t
DH
Configuration
Duty cycle stabilizer enabled
Duty cycle stabilizer disabled
Twos complement enabled
Offset binary enabled
Outputs in high impedance
Outputs enabled
Chip in power-down or
standby
Normal operation
A12
t
HIGH
A11
t
Figure 72. Serial Port Interface Timing Diagram
LOW
A10
A9
Rev. B | Page 39 of 72
t
CLK
A8
A7
SPI ACCESSIBLE FEATURES
Brief descriptions of the general features available on many
Analog Devices, Inc., high speed ADCs, including the AD9600,
that are accessible via the SPI are included in Table 21. These
features are described in detail in the AN-877 Application Note,
Interfacing to High Speed ADCs via SPI. The AD9600 part-specific
features are described in the Memory Map Register Description
section.
Table 21. Features Accessible Using the SPI
Feature Name
Modes
Clock
Offset
Test I/O
Output Mode
Output Phase
Output Delay
VREF
D5
D4
Description
Allows the user to set either the power-down
mode or the standby mode
Allows the user to access the DCS via the SPI
Allows the user to digitally adjust the
converter offset
Allows the user to set the test modes to have
known data on the output bits
Allows the user to set up the outputs
Allows the user to set the output clock polarity
Allows the user to vary the DCO delay
Allows the user to set the reference voltage
D3
D2
D1
D0
t
H
DON’T CARE
AD9600
DON’T CARE