AD9600BCPZ-105 Analog Devices Inc, AD9600BCPZ-105 Datasheet - Page 26

• Manufacturer Part Number: AD9600BCPZ-105
• Description: IC,A/D CONVERTER,DUAL,10-BIT,CMOS,LLCC,64PIN
• Manufacturer: Analog Devices Inc

Specifications of AD9600BCPZ-105

• Number Of Bits: 10
• Sampling Rate (per Second): 105M
• Data Interface: Serial, SPI™
• Number Of Converters: 2
• Power Dissipation (max): 650mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LFCSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9600
External Reference Operation
The use of an external reference may be necessary to enhance
the gain accuracy of the ADC or to improve the thermal drift
characteristics. Figure 54 shows the typical drift characteristics
of the internal reference in 1.0 V mode.
When the SENSE pin is tied to AVDD, the internal reference is
disabled, allowing the use of an external reference. An internal
reference buffer loads the external reference with an equivalent
6 kΩ load (see Figure 15). The internal buffer generates the
positive and negative full-scale references for the ADC core.
Therefore, the external reference must be limited to a maximum
of 1.0 V.
CLOCK INPUT CONSIDERATIONS
For optimum performance, the AD9600 sample clock inputs
(CLK+ and CLK−) should be clocked with a differential signal.
The signal is typically ac-coupled into the CLK+ and CLK− pins
via a transformer or capacitors. These pins are biased internally
(see Figure 55) and require no external bias.
Clock Input Options
The AD9600 has a very flexible clock input structure. The clock
input can be a CMOS, LVDS, LVPECL, or sine wave signal.
Regardless of the type of signal being used, the jitter of the clock
source is of the most concern, as described in the Jitter
Considerations section.
Figure 56 and Figure 57 show preferred methods for clocking the
AD9600 (at clock rates of up to 625 MHz). A low jitter clock source
is converted from a single-ended signal to a differential signal
using either an RF balun or an RF transformer.
–0.5
–1.0
–1.5
–2.0
–2.5
2.5
2.0
1.5
1.0
0
–40
CLK+
2pF
Figure 55. Equivalent Clock Input Circuit
–20
Figure 54. Typical VREF Drift
0
TEMPERATURE (°C)
AVDD
1.2V
20
40
2pF
60
CLK–
80
Rev. B | Page 26 of 72
The RF balun configuration is recommended for clock
frequencies between 125 MHz and 625 MHz, and the RF
transformer is recommended for clock frequencies from 10 MHz
to 200 MHz. The back-to-back Schottky diodes across the
secondary transformer or balun limit clock excursions into the
AD9600 to approximately 0.8 V p-p differential.
This helps prevent the large voltage swings of the clock from
feeding through to other portions of the AD9600 while
preserving the fast rise and fall times of the signal that are
critical to low jitter performance.
If a low jitter clock source is not available, another option is to
ac-couple a differential PECL signal to the sample clock input
pins as shown in Figure 58. The AD9510/AD9511/AD9512/
AD9513/AD9514/AD9515
jitter performance.
A third option is to ac-couple a differential LVDS signal to the
sample clock input pins as shown in Figure 59. The AD9510/
AD9511/AD9512/AD9513/AD9514/AD9515 family of clock
drivers offer excellent jitter performance.
CLK+
CLK+
CLK–
CLK–
CLK+
CLK+
50kΩ
50kΩ
Figure 56. Transformer-Coupled Differential Clock (up to 200 MHz)
Figure 57. Balun-Coupled Differential Clock (up to 625 MHz)
Figure 59. Differential LVDS Sample Clock (up to 150 MSPS)
Figure 58. Differential PECL Sample Clock (up to 150 MSPS)
50Ω
0.1µF
50Ω
0.1µF
0.1µF
50kΩ
0.1µF
0.1µF
50kΩ
1nF
1nF
AD9510/AD9511/AD9512/
AD9510/AD9511/AD9512/
AD9513/AD9514/AD9515
AD9513/AD9514/AD9515
100Ω
ADT1-1WT, 1:1Z
Mini-Circuits
DRIVER
DRIVER
PECL
LVDS
XFMR
0.1µF
family of clock drivers offers excellent
240Ω
®
0.1µF
0.1µF
0.1µF
0.1µF
SCHOTTKY
SCHOTTKY
HSMS2822
HSMS2822
DIODES:
DIODES:
240Ω
100Ω
100Ω
0.1µF
0.1µF
0.1µF
0.1µF
CLK+
CLK–
AD9600
CLK+
CLK–
CLK+
CLK–
AD9600
CLK+
CLK–
ADC
AD9600
AD9600
ADC
ADC
ADC