AD9512/PCBZ Analog Devices Inc, AD9512/PCBZ Datasheet - Page 36
AD9512/PCBZ
Manufacturer Part Number
AD9512/PCBZ
Description
800MHz Clock Distribution Eval Bd.
Manufacturer
Analog Devices Inc
Datasheet
1.AD9512BCPZ-REEL7.pdf
(48 pages)
Specifications of AD9512/PCBZ
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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AD9512
Table 16. Serial Control Port Timing
Parameter
t
t
t
t
t
t
t
DS
DH
CLK
S
H
HI
LO
SCLK
SDIO
CSB
SCLK
SDIO
CSB
t
Description
Setup time between data and rising edge of SCLK
Hold time between data and rising edge of SCLK
Period of the clock
Setup time between CSB and SCLK
Hold time between CSB and SCLK
Minimum period that SCLK should be in a logic high state
Minimum period that SCLK should be in a logic low state
TIMING DIAGRAM FOR TWO SUCCESSIVE COMMUNICATION CYCLES. NOTE THAT CSB MUST
BE TOGGLED HIGH AND THEN LOW AT THE COMPLETION OF A COMMUNICATION CYCLE.
t
DS
S
16 INSTRUCTION BITS + 8 DATA BITS
COMMUNICATION CYCLE 1
BI N
t
HI
t
DH
Figure 38. Use of CSB to Define Communication Cycles
Figure 37. Serial Control Port Timing—Write
t
CLK
CSB TOGGLE INDICATES
Rev. A | Page 36 of 48
t
LO
CYCLE COMPLETE
BI N + 1
16 INSTRUCTION BITS + 8 DATA BITS
t
PWH
COMMUNICATION CYCLE 2
t
H
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