AD9467BCPZ-250 Analog Devices Inc, AD9467BCPZ-250 Datasheet - Page 7

• Manufacturer Part Number: AD9467BCPZ-250
• Description: 16 Bit 250 MSPS ADC
• Manufacturer: Analog Devices Inc

Specifications of AD9467BCPZ-250

• Number Of Bits: 16
• Sampling Rate (per Second): 250M
• Data Interface: Serial, SPI™
• Number Of Converters: 1
• Power Dissipation (max): 1.45W
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 72-VFQFN, CSP Exposed Pad
• Number Of Elements: 1
• Resolution: 16Bit
• Architecture: Pipelined
• Sample Rate: 250MSPS
• Input Polarity: Bipolar
• Input Type: Voltage
• Rated Input Volt: ±1.25V
• Differential Input: Yes
• Power Supply Requirement: Single
• Single Supply Voltage (typ): 1.8/3.3V
• Dual Supply Voltage (typ): Not RequiredV
• Dual Supply Voltage (min): Not RequiredV
• Dual Supply Voltage (max): Not RequiredV
• Power Dissipation: 1.45W
• Differential Linearity Error: ±1LSB(Typ)
• Integral Nonlinearity Error: ±3LSB(Typ)
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 72
• Package Type: LFCSP EP
• Input Signal Type: Differential
• Sampling Rate: 250MSPS
• Input Channel Type: Differential
• Supply Voltage Range - Analog: 1.7V To 1.9V
• Supply Voltage Range - Digital: 1.7V To 1.9V
• Supply Current: 31mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

SWITCHING SPECIFICATIONS
AVDD1 = 1.8 V, AVDD2 = 3.3 V, AVDD3 = 1.8 V, DRVDD = 1.8 V, specified maximum sampling rate, 2.5 V p-p differential input, 1.25 V
internal reference, AIN = −1.0 dBFS, DCS on, default SPI settings, unless otherwise noted.
Table 4.
Parameter
CLOCK
OUTPUT PARAMETERS
APERTURE
1
2
3
Timing Diagrams
See the
Can be adjusted via the SPI interface.
Measurements were made using a part soldered to FR-4 material.
Clock Rate
Clock Pulse Width High (t
Clock Pulse Width Low (t
Propagation Delay (t
Rise Time (t
Fall Time (t
DCO Propagation Delay (t
DCO to Data Delay (t
Wake-Up Time (Power-Down)
Pipeline Latency
Aperture Delay (t
Aperture Uncertainty (Jitter)
Out-of-Range Recovery Time
2
AN-835
1
D14–/D15– (MSB)
D14+/D15+ (MSB)
F
R
) (20% to 80%)
D0+/D1+ (MSB)
Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed.
D0–/D1– (MSB)
) (20% to 80%)
A
)
DCO+
DCO–
CLK+
CLK–
. .
.
2, 3
PD
SKEW
VIN±
)
)
CL
CPD
CH
)
)
)
N – 1
t
CH
D15
D1
Temp
Full
Full
Full
25°C
25°C
25°C
25°C
Full
Full
Full
25°C
25°C
25°C
t
CL
D14
D0
N
Figure 2. 16-Bit Output Data Timing
t
A
1/fs
D15
Min
−200
50
D1
t
CPD
t
t
SKEW
PD
Rev. B | Page 7 of 32
AD9467BCPZ-200
N + 1
D14
D0
Typ
3
200
200
3
1.2
60
1
2.5
2.5
100
16
D15
D1
N + 2
D14
D0
Max
200
+200
D15
D1
Min
−200
50
N + 3
D14
D0
AD9467BCPZ-250
D15
D1
60
1
Typ
2
2
3
200
200
3
100
16
1.2
N + 4
D14
D0
Max
250
+200
D15
D1
N + 5
D14
D0
Unit
MSPS
ns
ns
ns
ps
ps
ns
ps
ms
Clock cycles
ns
fs rms
Clock cycles
AD9467