AD9467BCPZ-250 Analog Devices Inc, AD9467BCPZ-250 Datasheet - Page 6

• Manufacturer Part Number: AD9467BCPZ-250
• Description: 16 Bit 250 MSPS ADC
• Manufacturer: Analog Devices Inc

Specifications of AD9467BCPZ-250

• Number Of Bits: 16
• Sampling Rate (per Second): 250M
• Data Interface: Serial, SPI™
• Number Of Converters: 1
• Power Dissipation (max): 1.45W
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 72-VFQFN, CSP Exposed Pad
• Number Of Elements: 1
• Resolution: 16Bit
• Architecture: Pipelined
• Sample Rate: 250MSPS
• Input Polarity: Bipolar
• Input Type: Voltage
• Rated Input Volt: ±1.25V
• Differential Input: Yes
• Power Supply Requirement: Single
• Single Supply Voltage (typ): 1.8/3.3V
• Dual Supply Voltage (typ): Not RequiredV
• Dual Supply Voltage (min): Not RequiredV
• Dual Supply Voltage (max): Not RequiredV
• Power Dissipation: 1.45W
• Differential Linearity Error: ±1LSB(Typ)
• Integral Nonlinearity Error: ±3LSB(Typ)
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 72
• Package Type: LFCSP EP
• Input Signal Type: Differential
• Sampling Rate: 250MSPS
• Input Channel Type: Differential
• Supply Voltage Range - Analog: 1.7V To 1.9V
• Supply Voltage Range - Digital: 1.7V To 1.9V
• Supply Current: 31mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9467
DIGITAL SPECIFICATIONS
AVDD1 = 1.8 V, AVDD2 = 3.3 V, AVDD3 = 1.8 V, DRVDD = 1.8 V, specified maximum sampling rate, 2.5 V p-p differential input, 1.25 V
internal reference, AIN = −1.0 dBFS, DCS on, default SPI settings, unless otherwise noted.
Table 3.
Parameter
CLOCK INPUTS (CLK+, CLK−)
LOGIC INPUTS (SCLK, CSB, SDIO)
LOGIC OUTPUT (SDIO)
DIGITAL OUTPUTS (D0+ to D15+, D0− to
1
2
3
See the
This is specified for LVDS and LVPECL only.
This depends on if SPIVDD is tied to a 1.8 V or 3.3 V supply.
Logic Compliance
Differential Input Voltage
Input Common-Mode Voltage
Input Resistance (Differential)
Input Capacitance
Logic 1 Voltage
Logic 0 Voltage
Input Resistance
Input Capacitance
Logic 1 Voltage (I
Logic 0 Voltage (I
D15−, DCO+, DCO−, OR+, OR−)
Logic Compliance
Differential Output Voltage (V
Output Offset Voltage (V
Output Coding (Default)
AN-835
1
Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed.
OH
OL
= 800 μA)
= 50 μA)
3
OS
2
)
OD
)
Temp
Full
Full
Full
Full
Full
25°C
25°C
Full
Full
25°C
25°C
Full
Min
250
1.2
1.125
247
Rev. B | Page 6 of 32
CMOS/LVDS/LVPECL
AD9467BCPZ-200
Typ
0.8
20
2.5
30
0.5
1.7/3.1
Offset binary
LVDS
Max
3.6
0.3
0.3
1.375
545
Min
250
1.2
1.125
247
CMOS/LVDS/LVPECL
AD9467BCPZ-250
Typ
0.8
20
2.5
30
0.5
1.7/3.1
LVDS
Offset binary
Max
3.6
0.3
0.3
1.375
545
Unit
mV p-p
V
kΩ
pF
V
V
kΩ
pF
V
V
mV
V