AD9273BSVZ-25 Analog Devices Inc, AD9273BSVZ-25 Datasheet
AD9273BSVZ-25
Specifications of AD9273BSVZ-25
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AD9273BSVZ-25 Summary of contents
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FEATURES 8 channels of LNA, VGA, AAF, and ADC Low noise preamplifier (LNA) Input-referred noise voltage = 1.26 nV/√Hz (gain = 21.3 dB MHz typical SPI-programmable gain = 15.6 dB/17.9 dB/21.3 dB Single-ended input; V maximum = 733 ...
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AD9273 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Product Highlights ........................................................................... 3 Specifications ..................................................................................... 4 AC Specifications .......................................................................... 4 Digital Specifications ................................................................... 8 Switching Specifications ...
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The AD9273 requires a LVPECL-/CMOS-/LVDS-compatible sample rate clock for full performance operation. No external reference or driver components are required for many applications. The ADC automatically multiplies the sample rate clock for the appropriate LVDS serial data rate. A data ...
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AD9273 SPECIFICATIONS AC SPECIFICATIONS AVDD1 = 1.8 V, AVDD2 = 3.0 V, DRVDD = 1.8 V, 1.0 V internal ADC reference, f high (default), PGA gain = 24 dB, GAIN− = 0.8 V, AAF LPF cutoff = f ANSI-644 LVDS ...
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Parameter Conditions Min AAF Bandwidth In range Tolerance Group Delay MHz to Variation 18 MHz, GAIN 1.6 V Input-Referred LNA gain = Noise Voltage 15.6 dB/ 17.9 dB/ 21.3 dB ...
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AD9273 1 Parameter Conditions Min GAIN ACCURACY 25°C Gain Law Confor < GAIN+ mance Error < 0.16 V 0.16 V < GAIN+ −1.6 < 1.44 V 1.44 V < GAIN+ < 1.6 V Linear Gain Error GAIN+ = ...
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Parameter Conditions Min I Full-channel AVDD2 mode CW Doppler mode with four channels enabled I DRVDD Total Power Includes output Dissipation drivers, full- channel mode, no signal CW Doppler mode with four channels enabled Power-Down Dissipation Standby Power Dissipation ...
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AD9273 DIGITAL SPECIFICATIONS AVDD1 = 1.8 V, AVDD2 = 3.0 V, DRVDD = 1.8 V, 1.0 V internal ADC reference, f Table 2. Parameter 1 CLOCK INPUTS (CLK+, CLK−) Logic Compliance 2 Differential Input Voltage Input Common-Mode Voltage Input Resistance ...
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SWITCHING SPECIFICATIONS AVDD1 = 1.8 V, AVDD2 = 3.0 V, DRVDD = 1.8 V, 1.0 V internal ADC reference, f Table 3. Parameter 1 2 CLOCK Clock Rate Clock Pulse Width High ( Clock Pulse Width Low (t ...
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AD9273 ADC TIMING DIAGRAMS N – 1 AIN t EH CLK– CLK+ t CPD DCO– DCO+ t FCO FCO– FCO DOUTx– DOUTx+ N – 1 AIN t EH CLK– CLK+ t CPD DCO– DCO+ t FCO FCO– FCO+ ...
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ABSOLUTE MAXIMUM RATINGS Table 4. With Parameter Respect To Electrical AVDD1 GND AVDD2 GND DRVDD GND GND GND AVDD2 AVDD1 AVDD2 DRVDD AVDD1 DRVDD Digital Outputs GND (DOUTx+, DOUTx−, DCO+, DCO−, FCO+, FCO−) CLK+, CLK−, GAIN+, GND GAIN− LI-x, LO-x, ...
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AD9273 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS PIN 1 LI-E 1 INDICATOR LG-E 2 AVDD2 3 AVDD1 4 LO-F 5 LOSW-F 6 LI-F 7 LG-F 8 AVDD2 9 AVDD1 10 LO-G 11 LOSW-G 12 LI-G 13 LG-G 14 AVDD2 15 AVDD1 ...
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Table 6. Pin Function Descriptions Pin No. TQFP BGA Name 0 N/A GND N/A B5, B6, B8, C5, GND C6, C7, C8, D5, D6, D7, D8, E1, E5, E6, E7, E8, E12, F2, F4, F6, F7, F9, F11, G1, G3, ...
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AD9273 Pin No. TQFP BGA Name 45 M11 DOUTA− 46 L11 DOUTA+ 48 K11 STBY 49 J11 PDWN 51 K12 SCLK 52 J12 SDIO 53 H12 CSB LOSW LO-A 62 ...
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TYPICAL PERFORMANCE CHARACTERISTICS MSPS MHz Ω, LNA gain = 21.3 dB, LNA bias = mid-high, PGA gain = 24 dB, AAF LPF cutoff = f SAMPLE IN S HPF = LPF ...
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AD9273 500k 450k 400k 350k 300k 250k 200k 150k 100k 50k 0 –7 –6 –5 –4 –3 –2 – CODES Figure 12. Output-Referred Noise Histogram, GAIN+ = 0.0 V 200k 180k 160k 140k 120k 100k 80k 60k 40k ...
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GAIN+ = 1.6V 75 GAIN+ = 0.8V GAIN FREQUENCY (MHz) Figure 18. Antialiasing Filter (AAF) Group Delay Response 0 –10 –20 –30 –40 –50 GAIN+ = ...
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AD9273 5.00MHz, = 5.01MHz IN1 IN2 FUND2 LEVEL = FUND1 LEVEL – 20dB –20 –40 –60 GAIN –80 –100 –120 –40 –35 –30 –25 –20 –15 FUND1 LEVEL (dBFS) Figure 24. IMD3 vs. Fundamental ...
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EQUIVALENT CIRCUITS AVDDx V CM 15kΩ LI-x, LG-x Figure 25. Equivalent LNA Input Circuit 10Ω LO-x, LOSW-x Figure 26. Equivalent LNA Output Circuit 10Ω CLK+ 10kΩ 10kΩ 10Ω CLK– Figure 27. Equivalent Clock Input Circuit AVDDx 1.25V Rev ...
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AD9273 100Ω RBIAS Figure 31. Equivalent RBIAS Circuit AVDDx 70kΩ 1kΩ CSB Figure 32. Equivalent CSB Input Circuit VREF 6kΩ Figure 33. Equivalent VREF Circuit AVDDx Rev Page AVDD2 50Ω GAIN+ Figure 34. Equivalent GAIN+ ...
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THEORY OF OPERATION ULTRASOUND The primary application for the AD9273 is medical ultrasound. Figure 37 shows a simplified block diagram of an ultrasound system. A critical function of an ultrasound system is the time gain control (TGC) compensation for physiological ...
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AD9273 R FB1 FB2 T/R SWITCH CHANNEL OVERVIEW Each channel contains both a TGC signal path and a CW Doppler signal path. Common to both signal paths, the LNA provides user- ...
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Active Impedance Matching The LNA consists of a single-ended voltage gain amplifier with differential outputs and the negative output available externally. For example, with a fixed gain of 8× (17.9 dB), an active input termination is synthesized by connecting a ...
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AD9273 LNA Noise The short-circuit noise voltage (input-referred noise impor- tant limit on system performance. The short-circuit input-referred noise voltage for the LNA is 1.4 nV/√ gain of 21.3 dB, including the VGA noise at a ...
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INPUT OVERDRIVE Excellent overload behavior is of primary importance in ultrasound. Both the LNA and VGA have built-in overdrive protection and quickly recover after an overload event. Input Overload Protection As with any amplifier, voltage clamping prior to the inputs ...
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AD9273 AD9273 g LNA m g LNA m SWITCH ARRAY 8 × CHANNEL g LNA m g LNA m AD9273 g LNA m g LNA m SWITCH ARRAY 8 × CHANNEL g LNA m LNA g m Figure 45. Typical ...
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Crosspoint Switch Each LNA is followed by a transconductance amp for voltage- to-current conversion. Currents can be routed to one of eight pairs of differential outputs single-ended outputs for summing. Each CWD output pin sinks 2.4 mA ...
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AD9273 Table 9. Sensitivity and Dynamic Range of Trade-Offs LNA Gain Input-Referred Full-Scale Input Noise Voltage (V/V) (dB) (V p-p) (nV/√Hz) 6 15.6 0.733 1.6 8 17.9 0.550 1.42 12 21.3 0.367 1.26 1 LNA: output full scale = 4.4 ...
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PGA GAIN = 21dB 0.5 PGA GAIN = 24dB 0.4 0.3 0.2 PGA GAIN = 27dB 0.1 PGA GAIN = 30dB 0 0 0.2 0.4 0.6 0.8 1.0 GAIN+ (V) Figure 49. LNA with 17.9 dB Gain Setting/VGA Full-Scale ...
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AD9273 499Ω AD9273 ±0.4VDC AT 100Ω 0.8V CM GAIN+ 0.01µF AD8138 100Ω GAIN– ±0.4VDC AT 0.01µF 0.8V CM 499Ω Figure 53. Differential GAIN± Pins Configuration VGA Noise In a typical application, a VGA compresses a wide dynamic range input signal ...
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ADC The AD9273 uses a pipelined ADC architecture. The quantized output from each stage is combined into a 12-bit result in the digital correction logic. The pipelined architecture permits the first stage to operate on a new input sample and ...
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AD9273 The duty cycle stabilizer uses a delay-locked loop (DLL) to create the nonsampling edge result, any changes to the sampling frequency require approximately eight clock cycles to allow the DLL to acquire and lock to the new ...
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By asserting the PDWN pin high, the AD9273 is placed into power-down mode. In this state, the device typically dissipates 2 mW. During power-down, the LVDS output drivers are placed into a high impedance state. The AD9273 returns to normal ...
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AD9273 600 EYE: ALL BITS 400 200 100 0 –100 –200 –400 –600 –1.5ns –1.0ns –0.5ns 0ns –200ps –100ps 0ps Figure 65. Data Eye for LVDS Outputs in ANSI-644 Mode with Trace Lengths of ...
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EYE: ALL BITS 400 200 0 –200 –400 –600 –1.5ns –1.0ns –0.5ns 0ns –200ps –100ps 0ps Figure 67. Data Eye for LVDS Outputs in ANSI-644 Mode with 100 Ω Termination Resistor and Trace ...
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AD9273 When using the serial port interface (SPI), the DCO± phase can be adjusted in 60° increments relative to the data edge. This enables the user to refine system timing margins if required. The default DCO± timing, as shown in ...
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Power and Ground Recommendations When connecting power to the AD9273 recommended that two separate 1.8 V supplies be used: one for analog (AVDD) and one for digital (DRVDD). If only one 1.8 V supply is available, it should ...
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AD9273 SERIAL PORT INTERFACE (SPI) The AD9273 serial port interface allows the user to configure the signal chain for specific functions or operations through a structured register space provided inside the chip. This offers the user added flexibility and customization ...
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This interface is flexible enough to be controlled by either serial PROMS or PIC mirocontrollers. This provides the user with an alternative method, other than a full SPI controller, for programming the device (see the AN-812 Application Note ...
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AD9273 MEMORY MAP READING THE MEMORY MAP TABLE Each row in the memory map table has eight address locations. The memory map is roughly divided into three sections: the chip configuration register map (Address 0x00 to Address 0x02), the device ...
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Table 17. AD9273 Memory Map Register Addr. Bit 7 (Hex) Register Name (MSB) Bit 6 Chip Configuration Registers 00 CHIP_PORT_CONFIG 0 LSB first off (default) 01 CHIP_ID 02 CHIP_GRADE X X Device Index and Transfer ...
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AD9273 Addr. Bit 7 (Hex) Register Name (MSB) Bit 6 0F FLEX_CHANNEL_ Filter cutoff frequency control INPUT 0000 = 1.3 × 1/3 × f 0001 = 1.2 × 1/3 × f 0010 = 1.1 × 1/3 × f 0011 = ...
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Addr. Bit 7 (Hex) Register Name (MSB) Bit 6 19 USER_PATT1_LSB USER_PATT1_MSB B15 B14 1B USER_PATT2_LSB USER_PATT2_MSB B15 B14 21 SERIAL_CONTROL LSB first off (default) 22 SERIAL_CH_STAT X ...
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AD9273 OUTLINE DIMENSIONS 1.20 0.75 MAX 0.60 0.45 0° MIN 1.05 0.20 1.00 0.09 0.95 7° 3.5° 0.15 0° SEATING 0.05 0.08 MAX PLANE COPLANARITY VIEW A ROTATED 90 ° CCW BALL A1 INDICATOR TOP VIEW DETAIL A 1.40 MAX ...
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... AD9273BSVZ-50 −40°C to +85°C AD9273BSVZRL-50 1 −40°C to +85°C 1 AD9273BSVZ-40 −40°C to +85°C 1 AD9273BSVZRL-40 −40°C to +85°C 1 AD9273BSVZ-25 −40°C to +85°C 1 AD9273BSVZRL-25 −40°C to +85°C 1 AD9273BBCZ-25 −40°C to +85°C 1 AD9273BBCZ-40 −40°C to +85°C 1 AD9273BBCZ-50 − ...
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AD9273 NOTES Rev Page ...
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NOTES Rev Page AD9273 ...
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AD9273 NOTES ©2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07030-0-7/09(B) Rev Page ...