AD9228ABCPZRL7-65 Analog Devices Inc, AD9228ABCPZRL7-65 Datasheet - Page 32

• Manufacturer Part Number: AD9228ABCPZRL7-65
• Description: Quad 12-bit 65 MSPS Serial LVDS ADCPBFre
• Manufacturer: Analog Devices Inc

Specifications of AD9228ABCPZRL7-65

• Number Of Bits: 12
• Sampling Rate (per Second): 65M
• Data Interface: Serial, SPI™
• Number Of Converters: 4
• Power Dissipation (max): 510mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-VFQFN, CSP Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9228
Table 15. Serial Timing Definitions
Parameter
t
t
t
t
t
t
t
t
t
SCLK
SDIO
DS
DH
CLK
S
H
HI
LO
EN_SDIO
DIS_SDIO
CSB
DON’T CARE
DON’T CARE
1.800
1.795
1.790
1.785
1.780
1.775
1.770
1.765
1.760
1.755
1.750
1.745
1.740
1.735
1.730
1.725
1.720
1.715
0
10
NUMBER OF SDIO PINS CONNECTED TOGETHER
t
S
20
R/W
Figure 68. SDIO Pin Loading
Timing (Minimum, ns)
5
2
40
5
2
16
16
10
10
30
t
DS
W1
40
W0
50
t
DH
60
A12
70
A11
t
80
HI
Description
Setup time between the data and the rising edge of SCLK
Hold time between the data and the rising edge of SCLK
Period of the clock
Setup time between CSB and SCLK
Hold time between CSB and SCLK
Minimum period that SCLK should be in a logic high state
Minimum period that SCLK should be in a logic low state
Minimum time for the SDIO pin to switch from an input to an output relative to the SCLK
falling edge (not shown in Figure 69)
Minimum time for the SDIO pin to switch from an output to an input relative to the SCLK
rising edge (not shown in Figure 69)
90
A10
Figure 69. Serial Timing Details
t
100
LO
A9
Rev. D | Page 32 of 56
t
CLK
A8
A7
If the user chooses not to use the SPI, these dual-function pins
serve their secondary functions when the CSB is strapped to
AVDD during device power-up. See the Theory of Operation
section for details on which pin-strappable functions are
supported on the SPI pins.
For users who wish to operate the ADC without using the
SPI, remove any connections from the CSB, SCLK/DTP, and
SDIO/ODM pins. By disconnecting these pins from the control
bus, the ADC can function in its most basic operation. Each
of these pins has an internal termination that floats to its
respective level.
D5
D4
D3
D2
D1
D0
t
H
DON’T CARE
DON’T CARE