AD9117-DPG2-EBZ Analog Devices Inc, AD9117-DPG2-EBZ Datasheet - Page 32

• Manufacturer Part Number: AD9117-DPG2-EBZ
• Description: Dual 14B, Low Power D-A Converter
• Manufacturer: Analog Devices Inc

Specifications of AD9117-DPG2-EBZ

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9114/AD9115/AD9116/AD9117
THEORY OF OPERATION
Figure 84 shows a simplified block diagram of the AD9114/
AD9115/AD9116/AD9117 that consists of two DACs, digital
control logic, and a full-scale output current control. Each DAC
contains a PMOS current source array capable of providing a
maximum of 20 mA. The arrays are divided into 31 equal currents
that make up the five most significant bits (MSBs). The next four
bits, or middle bits, consist of 15 equal current sources whose
value is 1/16 of an MSB current source. The remaining LSBs are
binary weighted fractions of the current sources of the middle
bits. Implementing the middle and lower bits with current sources,
instead of an R-2R ladder, enhances its dynamic performance for
multitone or low amplitude signals and helps maintain the high
output impedance of the main DACs (that is, >200 MΩ).
The current sources are switched to one or the other of the two
output nodes (I
The switches are based on the architecture that was pioneered in
the AD976x family, with further refinements to reduce distortion
contributed by the switching transient. This switch architecture also
reduces various timing errors and provides matching complementary
drive signals to the inputs of the differential current switches.
The analog and digital I/O sections of the AD9114/AD9115/
AD9116/AD9117 have separate power supply inputs (AVDD and
DVDDIO) that can operate independently over a 1.8 V to 3.3 V
range. The core digital section requires 1.8 V. An optional on-chip
LDO is provided for DVDDIO supplies greater than 1.8 V, or the
OUTP
or I
DVDDIO
OUTN
DVDD
DVSS
DB11
DB10
DB9
DB8
DB7
DB6
DB5
) via PMOS differential current switches.
1.8V
LDO
INTERLEAVED
INTERFACE
1 INTO 2
INTERFACE
DATA
SPI
100µA
Figure 84. Simplified Block Diagram
I
REF
Q DATA
I DATA
BAND
QR
1V
GAP
Rev. A | Page 32 of 80
2kΩ
SET
10kΩ
CLOCK
DIST
1.8 V can be supplied directly through DVDD. A 1.0 μF bypass
capacitor at DVDD (Pin 7) is required when using the LDO.
The core is capable of operating at a rate of up to 125 MSPS. It
consists of edge-triggered latches and the segment decoding logic
circuitry. The analog section includes PMOS current sources,
associated differential switches, a 1.0 V band gap voltage
reference, and a reference control amplifier.
Each DAC full-scale output current is regulated by the reference
control amplifier and can be set from 4 mA to 20 mA via an
external resistor, xR
(FSADJx).
The external resistor, in combination with both the reference control
amplifier and voltage reference, V
which is replicated to the segmented current sources with the proper
scaling factor. The full-scale current, I
Optional on-chip xR
programmed between a nominal value of 1.6 kΩ to 8 kΩ (4 mA
to 20 mA I
The AD9114/AD9115/AD9116/AD9117 provide the option of
setting the output common mode to a value other than AGND via
the output common-mode pin (CMLI and CMLQ). This facilitates
directly interfacing the output of the AD9114/AD9115/AD9116/
AD9117 to components that require common-mode levels greater
than 0 V.
AUX1DAC
AUX2DAC
IR
2kΩ
SET
xOUTFS
AD9117
Q DAC
I DAC
, respectively).
60Ω TO
60Ω TO
QR
260Ω
260Ω
IR
SET
CM
CM
SET
, connected to its full-scale adjust pin
resistors are provided that can be
62.5Ω
62.5Ω
62.5Ω
62.5Ω
REFIO
, sets the reference current, I
xOUTFS
RLIN
IOUTN
IOUTP
RLIP
AVDD
AVSS
RLQP
QOUTP
QOUTN
RLQN
, is 32 × I
xREF
.
xREF
,