AD8195ACPZ-R7 Analog Devices Inc, AD8195ACPZ-R7 Datasheet - Page 12

• Manufacturer Part Number: AD8195ACPZ-R7
• Description: Front Panel HDMI Buffer
• Manufacturer: Analog Devices Inc

Specifications of AD8195ACPZ-R7

• Function: Switch
• Circuit: 1 x 1:1
• Voltage Supply Source: Single Supply
• Voltage - Supply, Single/dual (±): 3 V ~ 3.6 V
• Current - Supply: 40mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 40-VFQFN, CSP Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD8195
THEORY OF OPERATION
INTRODUCTION
The primary function of the AD8195 is to buffer a single (HDMI
or DVI) link. The HDMI or DVI link consists of four differential,
high speed channels and three auxiliary single-ended, low speed
control signals. The high speed channels include a data-word clock
and three transition minimized differential signaling (TMDS)
data channels running at 10× the data-word clock frequency for
data rates up to 2.25 Gbps. The three low speed control signals
consist of the display data channel (DDC) bus (SDA and SCL)
and the consumer electronics control (CEC) line.
All four high speed TMDS channels are identical; that is, the
pixel clock can be run on any of the four TMDS channels.
Receive channel compensation is provided for the high speed
channels to support long input cables. The AD8195 also
includes selectable preemphasis for driving high loss output
cables.
In the intended application, the AD8195 would be placed between
a source and a sink, with long cable runs on the input and output.
INPUT CHANNELS
Each high speed input differential pair terminates to the
3.3 V VTTI power supply through a pair of single-ended 50 Ω
on-chip resistors, as shown in Figure 26. When the transmitter
of the AD8195 is disabled by setting the TX_EN control pin, the
input termination resistors are also disabled to provide a high
impedance node at the TMDS inputs.
The input equalizer provides 12 dB of high frequency boost.
No specific cable length is suggested for this equalization level
because cable performance varies widely between manufacturers;
however, in general, the AD8195 does not degrade or over-
equalize input signals, even for short input cables. The AD8195
can equalize more than 20 meters of 24 AWG cable at 2.25 Gbps,
over reference cables that exhibit an insertion loss of −15 dB.
IPx
INx
Figure 26. High Speed Input Simplified Schematic
AVEE
VTTI
50Ω
50Ω
CABLE
TX_EN
EQ
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OUTPUT CHANNELS
Each high speed output differential pair is terminated to the
3.3 V VTTO power supply through two single-ended 50 Ω
on-chip resistors (see Figure 27).
The output termination resistors of the AD8195 back terminate
the output TMDS transmission lines. These back terminations,
as recommended in the HDMI 1.3a specification, act to absorb
reflections from impedance discontinuities on the output traces,
improving the signal integrity of the output traces and adding
flexibility to how the output traces can be routed. For example,
interlayer vias can be used to route the AD8195 TMDS outputs
on multiple layers of the PCB without severely degrading the
quality of the output signal.
The AD8195 has an external control pin, TX_EN, that disables
the transmitter, reducing power when the transmitter is not in
use. Additionally, when the transmitter is disabled, the input
termination resistors are also disabled to present a high
impedance state at the input and indicate to any connected
HDMI sources that the link through the AD8195 is inactive.
Table 7. Transmitter Enable Setting
TX_EN
0
1
The AD8195 also includes two levels of programmable output
preemphasis, 0 dB and 6 dB. The output preemphasis level can
be manually configured by setting the PE_EN pin. No specific
cable length is suggested for use with either preemphasis setting,
as cable performance varies widely among manufacturers.
Table 8. Preemphasis Setting
PE_EN
0
1
Figure 27. High Speed Output Simplified Schematic
OPx
Function
Tx/input termination disabled
Tx/input termination enabled
50Ω
VTTO
AVEE
PE Boost
0 dB
6 dB
I
OUT
50Ω
ONx