AD7147AACBZ-RL Analog Devices Inc, AD7147AACBZ-RL Datasheet - Page 29

• Manufacturer Part Number: AD7147AACBZ-RL
• Description: CAPACITANCE TO DIGITAL CONVERTER
• Manufacturer: Analog Devices Inc
• Series: CapTouch™r
• Type: Capacitive Sensor Controllerr

Specifications of AD7147AACBZ-RL

• Resolution (bits): 16 b
• Data Interface: Serial, SPI™
• Voltage Supply Source: Single Supply
• Voltage - Supply: 2.6 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 25-WLCSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Sampling Rate (per Second): -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

GPIO INT OUTPUT CONTROL
The INT output signal can be controlled by the GPIO pin when
the GPIO is configured as an input. The GPIO is configured as
an input by setting the GPIO_SETUP bits in the interrupt enable
register to 01. See the
section for more information on how to configure the GPIO.
Enable the GPIO interrupt by setting the GPIO_INT_ENABLE
bit in Register 0x007 to 1, or disable the GPIO interrupt by
clearing this bit to 0. The GPIO status bit in the conversion-
complete interrupt status register reflects the status of the GPIO
Table 16. GPIO Interrupt Behavior
GPIO_INPUT_CONFIG
00 = Negative Level Triggered
00 = Negative Level Triggered
01 = Positive Edge Triggered
01 = Positive Edge Triggered
10 = Negative Edge Triggered
10 = Negative Edge Triggered
11 = Positive Level Triggered
11 = Positive Level Triggered
General-Purpose Input/Output (GPIO)
GPIO Pin
1
0
1
0
1
0
1
0
1
0
GPIO_INT_STATUS
0
1
0
1
1
0
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interrupt. This bit is set to 1 when the GPIO has triggered INT .
The bit is cleared upon reading the GPIO_INT_STATUS bit if the
condition that caused the interrupt is no longer present.
The GPIO interrupt can be set to trigger on a rising edge, falling
edge, high level, or low level at the GPIO input pin. Table 16 shows
how the settings of the GPIO_INPUT_CONFIG bits in the inter-
rupt enable (STAGE_LOW_INT_ENABLE) register affect the
behavior of INT .
Figure 42 to Figure 45 show how the interrupt output is cleared
upon a read from the GPIO_INT_STATUS bit.
0
0
1
0
INT
1
1
0
1
INT Behavior
Not triggered
Asserted while signal on GPIO pin is low
Pulses low at low-to-high GPIO transition
Not triggered
Pulses low at high-to-low GPIO transition
Not triggered
Asserted while signal on GPIO pin is high
Not triggered
AD7147A