AD5722AREZ Analog Devices Inc, AD5722AREZ Datasheet - Page 24

• Manufacturer Part Number: AD5722AREZ
• Description: Dual 12Bit DAC 1 LSB INL
• Manufacturer: Analog Devices Inc

Specifications of AD5722AREZ

• Design Resources: Software Configurable 12-Bit Dual-Channel Unipolar/Bipolar Voltage Output Using AD5722 (CN0094)
• Settling Time: 10µs
• Number Of Bits: 12
• Data Interface: Serial
• Number Of Converters: 2
• Voltage Supply Source: Analog and Digital, Dual ±
• Power Dissipation (max): 190mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-TSSOP Exposed Pad, 24-eTSSOP, 24-HTSSOP
• Number Of Channels: 2
• Resolution: 12b
• Interface Type: Serial (3-Wire, SPI, QSPI, Microwire)
• Single Supply Voltage (typ): 5/9/12/15V
• Dual Supply Voltage (typ): ±5/±9/±12/±15V
• Architecture: Resistor-String
• Power Supply Requirement: Single/Dual
• Output Type: Voltage
• Integral Nonlinearity Error: ±1LSB
• Single Supply Voltage (min): 4.5V
• Single Supply Voltage (max): 16.5V
• Dual Supply Voltage (min): ±4.5V
• Dual Supply Voltage (max): ±16.5V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 24
• Package Type: TSSOP EP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD5722/AD5732/AD5752
INPUT SHIFT REGISTER
The input shift register is 24 bits wide and consists of a read/write bit (R/ W ), a reserved bit (zero) that must always be set to 0, three
register select bits (REG0, REG1, REG2), three DAC address bits (A2, A1, A0), and 16 data bits (data). The register data is clocked in MSB
first on the SDIN pin. Table 16 shows the register format, and Table 17 describes the function of each bit in the register. All registers are
read/write registers.
Table 16. Input Register Format
MSB
DB23
R/W
Table 17. Input Register Bit Functions
Bit Mnemonic
R/W
REG2, REG1, REG0
A2, A1, A0
Data
DB22
Zero
Description
Indicates a read from or a write to the addressed register.
Used in association with the address bits to determine if a write operation is to the DAC register, the output range
select register, the power control register, or the control register.
REG2
0
0
0
0
These DAC address bits are used to decode the DAC channels.
A2
0
0
1
Data bits.
DB21
REG2
REG1
0
0
1
1
A1
0
1
0
DB20
REG1
REG0
0
1
0
1
A0
0
0
0
Function
DAC register
Output range select register
Power control register
Control register
Channel Address
DAC A
DAC B
Both DACs
Rev. C | Page 24 of 32
DB19
REG0
DB18
A2
DB17
A1
DB16
A0
DB15 to DB0
Data
LSB