AD5532ABC-2 Analog Devices Inc, AD5532ABC-2 Datasheet - Page 14

• Manufacturer Part Number: AD5532ABC-2
• Description: IC,Sample/Track-and-Hold Amplifier,32-CHANNEL,CMOS,BGA,74PIN,PLASTIC
• Manufacturer: Analog Devices Inc

Specifications of AD5532ABC-2

• Rohs Status: RoHS non-compliant
• Settling Time: 30µs
• Number Of Bits: 14
• Data Interface: Serial
• Number Of Converters: 34
• Voltage Supply Source: Analog and Digital
• Power Dissipation (max): 623mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 74-CSPBGA
• Number Of Channels: 32
• Resolution: 14b
• Conversion Rate: 45KSPS
• Interface Type: PARALLEL/SERIAL 3W
• Single Supply Voltage (typ): Not RequiredV
• Dual Supply Voltage (typ): ±9/5/±12/5/±15/5V
• Power Supply Requirement: Dual
• Output Type: Voltage
• Single Supply Voltage (min): Not RequiredV
• Single Supply Voltage (max): Not RequiredV
• Dual Supply Voltage (min): -4.75/8/4.75V
• Dual Supply Voltage (max): ±16.5/5.25V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 74
• For Use With: EVAL-AD5532HSEBZ - BOARD EVAL FOR AD5532HSEVAL-AD5532EBZ - BOARD EVAL FOR AD5532
• Lead Free Status / Rohs Status: Not Compliant

AD5532
FUNCTIONAL DESCRIPTION
The AD5532 consists of 32 DACs and an ADC (for ISHA
mode) in a single package. In DAC mode, a 14-bit digital word
is loaded into one of the 32 DAC Registers via the serial
interface. This is then converted (with gain and offset) into an
analog output voltage (V
To update a DAC’s output voltage, the required DAC is
addressed via the serial port. When the DAC address and code
have been loaded, the selected DAC converts the code.
At power-on, all the DACs, including the offset channel, are
loaded with zeros. Each of the 33 DACs is offset internally by
50 mV (typ) from GND, so the outputs V
50 mV (typ) at power-on if the OFFS_IN pin is driven directly
by the on-board offset channel (OFFS_OUT), i.e. if OFFS_IN is
50 mV, V
OUTPUT BUFFER STAGE—GAIN AND OFFSET
The function of the output buffer stage is to translate the 50
mV–3 V output of the DAC to a wider range. This is done by
gaining up the DAC output by 3.52/7 and offsetting the voltage
by the voltage on OFFS_IN pin.
AD5532-1/AD5532-3/AD5532-5:
AD5532-2:
V
V
The following table shows how the output range on V
to the offset voltage supplied by the user.
Table 8. Sample Output Voltage Ranges
V
(V)
0.5
1
V
V
OFFSET VOLTAGE CHANNEL
The offset voltage can be externally supplied by the user at
OFFS_IN or it can be supplied by an additional offset voltage
channel on the device itself. The offset can be set up in two
ways. In ISHA mode, the required offset voltage is set up on V
and acquired by the offset channel. In DAC mode, the code
corresponding to the offset value is loaded directly into the
offset DAC. This offset channel’s DAC output is directly
connected to OFFS_OUT. By connecting OFFS_OUT to
OFFS_IN
DAC
OFFS_IN
OUT
OUT
V
V
OUT
OUT
is the output of the DAC.
is limited only by the headroom of the output amplifiers.
must be within maximum ratings.
is the voltage at the OFFS_IN pin.
=
=
OUT
7
. 3
V
(V)
0.05 to 3
0.05 to 3
52
×
DAC
= (Gain × V
V
×
DAC
V
DAC
−
6
V
(AD5532-1/-3/-5)
−1.26 to +9.3
−2.52 to +8.04
−
OUT
OUT
×
DAC
. 2
V
0–V
) – (Gain – 1) ×V
52
OFFS
×
OUT
_
IN
V
31).
OFFS
_
IN
OUT
V
(AD5532-2)
Headroom limited
−6 to +15
0 to V
OUT
OFFS_IN
OUT
= 50 mV.
OUT
31 are
relates
Rev. D | Page 14 of 20
IN
OFFS_IN this offset voltage can be used as the offset voltage for
the 32 output amplifiers. It is important to choose the offset so
that V
RESET FUNCTION
The reset function on the AD5532 can be used to reset all
nodes on this device to their power-on reset condition. This is
implemented by applying a low-going pulse of between 90 ns
and 200 ns to the TRACK / RESET pin on the device. If the
applied pulse is less than 90 ns, it is assumed to be a glitch
and no operation takes place. If the applied pulse is wider
than 200 ns, this pin adopts its track function on the selected
channel, V
on the channel does not occur until a rising edge of TRACK .
ISHA MODE
In ISHA mode, the input voltage V
into a digital word. The noninverting input to the output buffer
(gain and offset stage) is tied to V
period to avoid spurious outputs, while the DAC acquires the
correct code. This is completed in 16 μs max. The updated DAC
output then assumes control of the output voltage. The output
voltage of the DAC is connected to the noninverting input of
the output buffer. Because the channel output voltage is
effectively the output of a DAC, there is no droop associated
with it. As long as power is maintained to the device, the output
voltage is constant until this channel is addressed again.
Because the internal DACs are offset by 70 mV (max) from
GND, the minimum V
maximum V
(max).
ANALOG INPUT (ISHA MODE)
Figure 19 shows the equivalent analog input circuit. The
Capacitor C1 is typically 20 pF and can be attributed to pin
capacitance and 32 off-channels. When a channel is selected, an
extra 7.5 pF (typ) is switched in. This Capacitor C2 is charged
to the previously acquired voltage on that particular channel so
it must charge/discharge to the new level. The external source
must be able to charge/discharge this additional capacitance
within 1 μs–2 μs of channel selection so that V
acquired accurately. Thus, a low impedance source is suggested.
Large source impedances significantly affect the performance
of the ADC. An input buffer amplifier may be required.
OUT
is within maximum ratings.
IN
IN
V
is switched to the output buffer, and an acquisition
IN
is 2.96 V due to the upper dead band of 40 mV
Figure 19. Analog Input Circuit
IN
C1
20pF
in ISHA mode is 70 mV. The
IN
IN
ADDRESSED CHANNEL
during the acquisition
is sampled and converted
C2
7.5pF
IN
can be