AD5532ABC-2 Analog Devices Inc, AD5532ABC-2 Datasheet - Page 12

• Manufacturer Part Number: AD5532ABC-2
• Description: IC,Sample/Track-and-Hold Amplifier,32-CHANNEL,CMOS,BGA,74PIN,PLASTIC
• Manufacturer: Analog Devices Inc

Specifications of AD5532ABC-2

• Rohs Status: RoHS non-compliant
• Settling Time: 30µs
• Number Of Bits: 14
• Data Interface: Serial
• Number Of Converters: 34
• Voltage Supply Source: Analog and Digital
• Power Dissipation (max): 623mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 74-CSPBGA
• Number Of Channels: 32
• Resolution: 14b
• Conversion Rate: 45KSPS
• Interface Type: PARALLEL/SERIAL 3W
• Single Supply Voltage (typ): Not RequiredV
• Dual Supply Voltage (typ): ±9/5/±12/5/±15/5V
• Power Supply Requirement: Dual
• Output Type: Voltage
• Single Supply Voltage (min): Not RequiredV
• Single Supply Voltage (max): Not RequiredV
• Dual Supply Voltage (min): -4.75/8/4.75V
• Dual Supply Voltage (max): ±16.5/5.25V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 74
• For Use With: EVAL-AD5532HSEBZ - BOARD EVAL FOR AD5532HSEVAL-AD5532EBZ - BOARD EVAL FOR AD5532
• Lead Free Status / Rohs Status: Not Compliant

AD5533
Reset Function
The reset function on the AD5533 can be used to reset all nodes
on this device to their power-on-reset condition. This is imple-
mented by applying a low-going pulse of between 90 ns and 200 ns
to the TRACK/RESET Pin on the device. If the applied pulse
is less than 90 ns, it is assumed to be a glitch and no operation
takes place. If the applied pulse is wider than 200 ns, this pin adopts
its TRACK function on the selected channel, V
the output buffer, and an acquisition on the channel will not occur
until a rising edge of TRACK.
TRACK Function
Normally in the ISHA Mode of operation, TRACK is held high
and the channel begins to acquire when it is addressed. However,
if TRACK is low when the channel is addressed, V
to the output buffer and an acquisition on the channel will not
occur until a rising edge of TRACK. At this stage, the BUSY Pin
will go low until the acquisition is complete, at which point the
DAC assumes control of the voltage to the output buffer and
V
This is useful in an application where the user wants to ramp up
V
need to be acquired continuously while it is ramping up. TRACK
can be kept low and only when V
is TRACK brought high. At this stage, the acquisition of V
In the example shown, a desired voltage is required on the output
of the pin driver. This voltage is represented by one input to a
comparator. The µC/µP ramps up the input voltage on V
through a DAC. TRACK is kept low while the voltage on V
ramps up so that V
voltage is reached on the output of the pin driver, the comparator
output switches. The µC/µP then knows what code is required to
be input in order to obtain the desired voltage at the DUT. The
TRACK input is now brought high and the part begins to acquire
V
goes high, the output buffer is switched from V
of the DAC.
MODES OF OPERATION
The AD5533 can be used in three different modes. These modes
are set by two mode bits, the first two bits in the serial word.
The 01 option (DAC Mode) is not available for the AD5533.
To avail of this mode, refer to the AD5532 data sheet. If you
attempt to set up DAC Mode, the AD5533 will enter a Test Mode
and a 24-clock write will be necessary to clear this.
Mode Bit 1
0
0
1
1
IN
IN
IN
. BUSY goes low until V
until V
is free to change again without affecting this output value.
OUT
reaches a particular level (Figure 7). V
Table II. Modes of Operation
Mode Bit 2
0
1
0
1
IN
is not continually acquired. When the desired
IN
has been acquired. When BUSY
OUT
has reached its desired voltage
Operating Mode
ISHA Mode
DAC Mode (Not Available)
Acquire and Read Back
Read Back
IN
IN
to the output
is switched to
IN
IN
is switched
IN
does not
begins.
IN
IN
–12–
1. ISHA Mode
In this standard mode, a channel is addressed and that channel
acquires the voltage on V
to address the relevant channel (V
or all channels). MSB is written first.
2. Acquire and Readback Mode
This mode allows the user to acquire V
in a particular DAC Register. The relevant channel is addressed
(10-bit write, MSB first) and V
Following the acquisition, after the next falling edge of SYNC
the data in the relevant DAC Register is clocked out onto the
D
ignored. The full acquisition time must elapse before the DAC
register data can be clocked out.
3. Readback Mode
Again, this is a Readback Mode but no acquisition is performed.
The relevant channel is addressed (10-bit write, MSB first) and
on the next falling edge of SYNC, the data in the relevant DAC
Register is clocked out onto the D
The user must allow 400 ns (min) between the last SCLK falling
edge in the 10-bit write and the falling edge of SYNC in the 14-bit
read back. The serial write and read words can be seen in Figure 8.
This feature allows the user to read back the DAC Register code
of any of the channels. Read back is useful if the system has been
calibrated and the user wants to know what code in the DAC
corresponds to a desired voltage on V
INTERFACES
Serial Interface
The SER/PAR Pin is tied high to enable the serial interface and
to disable the parallel interface. The serial interface is controlled
by the four pins that follow.
OUT
SYNC, D
Standard 3-wire Interface Pins. The SYNC Pin is shared
with the CS function of the parallel interface.
D
Data Out Pin for reading back the contents of the DAC
Registers. The data is clocked out on the rising edge of SCLK
and is valid on the falling edge of SCLK.
CAL Bit
When this is high, all 32 channels acquire V
The acquisition time is then 45 µs (typ) and accuracy may be
reduced.
OFFSET_SEL Bit
If this bit is set high, the offset channel is selected and Bits
A4–A0 are ignored.
Test Bit
This must be set low for correct operation of the part.
A4–A0
Used to address any one of the 32 channels (A4 = MSB of
address, A0 = LSB).
DB13–DB0
These are used in both Readback Modes to read a 14-bit word
from the addressed DAC Register.
OUT
line in a 14-bit serial format. During read back D
IN
, SCLK
IN
. This mode requires a 10-bit write
IN
OUT
is acquired in 16 µs (max).
OUT
line in a 14-bit serial format.
OUT
0–V
IN
.
and read back the data
OUT
31, offset channel
IN
simultaneously.
IN
REV. A
is