74ALVCH16821DGG:11 NXP Semiconductors, 74ALVCH16821DGG:11 Datasheet - Page 2

• Manufacturer Part Number: 74ALVCH16821DGG:11
• Description: 74ALVCH16821DGG/TSSOP56/TUBE-B
• Manufacturer: NXP Semiconductors
• Series: 74ALVCHr
• Type: D-Type Busr

Specifications of 74ALVCH16821DGG:11

• Function: Standard
• Output Type: Tri-State Non Inverted
• Number Of Elements: 2
• Number Of Bits Per Element: 10
• Frequency - Clock: 250MHz
• Delay Time - Propagation: 2.6ns
• Trigger Type: Positive Edge
• Current - Output High, Low: 24mA, 24mA
• Voltage - Supply: 2.3 V ~ 2.7 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 56-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 74ALVCH16821DG; 74ALVCH16821DG; 935259010112

1.
FEATURES
QUICK REFERENCE DATA
GND = 0V; T
NOTE:
ORDERING INFORMATION
Philips Semiconductors
56-Pin Plastic SSOP Type III
56-Pin Plastic TSSOP Type II
1998 May 29
Wide supply voltage range of 1.2V to 3.6V
Complies with JEDEC standard no. 8-1A
Current drive
CMOS low power consumption
Direct interface with TTL levels
MULTIBYTE
Low inductance multiple V
and ground bounce
All data inputs have bus hold
Output drive capability 50 transmission lines @ 85 C
20-bit bus-interface D-type flip-flop;
positive-edge trigger (3-State)
t
C
C
C
F
PHL
SYMBOL
max
I
PD
C
P
f
f
S (C
i
o
D
PD
= input frequency in MHz; C
/t
= output frequency in MHz; V
PLH
= C
L
is used to determine the dynamic power dissipation (P
PD
amb
PACKAGES
V
CC
TM
= 25 C; t
V
2
24 mA at 3.0 V
flow-through standard pin-out architecture
Propagation delay
nCP to nQ
Input capacitance
Power dissipation capacitance per buffer
Power dissipation capacitance per buffer
Maximum clock frequency
CC
f
2
o
) = sum of outputs.
f
i
r
+ S (C
= t
CC
n
f
and ground pins for minimum noise
2.5ns
L
PARAMETER
L
= output load capacitance in pF;
V
CC
CC
TEMPERATURE RANGE
= supply voltage in V;
2
f
–40 C to +85 C
–40 C to +85 C
o
) where:
D
V
V
V = GND to V
V
V
V
in mW):
CC
CC
I
CC
CC
= GND to V
OUTSIDE NORTH AMERICA
= 2.5V, C
= 3.3V, C
= 2.5V, C
= 3.3V, C
2
74ALVCH16821 DGG
74ALVCH16821 DL
DESCRIPTION
The 74ALVCH16821 has two 10-bit, edge triggered registers, with
each register coupled to a 3-State output buffer. The two sections of
each register are controlled independently by the clock (nCP) and
Output Enable (nOE) control gates.
Each register is fully edge triggered. The state of each D input, one
set-up time before the Low-to-High clock transition, is transferred to
the corresponding flip-flop’s Q output.
When nOE is LOW, the data in the register appears at the outputs.
When nOE is HIGH, the outputs are in high impedance OFF state.
Operation of the nOE input does not affect the state of the flip-flops.
The 74ALVCH16821 has active bus hold circuitry which is provided
to hold unused or floating data inputs at a valid logic level. This
feature eliminates the need for external pull-up or pull-down
resistors.
L
L
L
L
CC
CC
= 30pF
= 50pF
= 30pF
= 50pF
1
1
CONDITIONS
Outputs enabled
Outputs disabled
NORTH AMERICA
ACH16821 DGG
ACH16821 DL
74ALVCH16821
TYPICAL
Product specification
250
350
2.6
2.5
5.0
33
17
DWG NUMBER
853-2066 19467
SOT371-1
SOT364-1
UNIT
MHz
pF
pF
pF
ns