5962-8773901XA National Semiconductor, 5962-8773901XA Datasheet - Page 9

• Manufacturer Part Number: 5962-8773901XA
• Description: LO PWR LO OFFSET VOLT QUAD COM
• Manufacturer: National Semiconductor

Specifications of 5962-8773901XA

• Number Of Elements: 4
• Output Type: Open Collector
• Technology: Bipolar
• Input Offset Voltage: 2@5VmV
• Single Supply Voltage (typ): 9/12/15/18/24/28V
• Dual Supply Voltage (typ): ±3/±5/±9/±12V
• Supply Current (max): 3@5VmA
• Common Mode Rejection Ratio: 70dB
• Voltage Gain In Db: 93.98dB
• Power Supply Rejection Ratio: 70dB
• Power Supply Requirement: Single/Dual
• Single Supply Voltage (min): 5V
• Single Supply Voltage (max): 30V
• Dual Supply Voltage (min): ±2.5V
• Dual Supply Voltage (max): ±15V
• Power Dissipation: 680mW
• Operating Temp Range: -55C to 125C
• Operating Temperature Classification: Military
• Mounting: Surface Mount
• Pin Count: 14
• Package Type: CPAK
• Lead Free Status / Rohs Status: Not Compliant

Note 2: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
functional, but do not guaranteed specific performance limits. For guaranteed specifications and test conditions, see, the Electrical Characteristics. The guaranteed
specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test
conditions.
Note 3: Short circuits from the output to V
current is approximately 20 mA independent of the magnitude of V
Note 4: This input current will only exist when the voltage at any of the input leads is driven negative. It is due to the collector-base junction of the input PNP
transistors becoming forward biased and thereby acting as input diode clamps. In addition to this diode action, there is also lateral NPN parasitic transistor action
on the IC chip. This transistor action can cause the output voltages of the comparators to go to the V
time duration that an input is driven negative. This is not destructive and normal output states will re-establish when the input voltage, which was negative, again
returns to a value greater than −0.3 V
Note 5: The low bias dissipation and the ON-OFF characteristics of the outputs keeps the chip dissipation very small (P
are allowed to saturate.
Note 6: The direction of the input current is out of the IC due to the PNP input stage. This current is essentially constant, independent of the state of the output
so no loading change exists on the reference or input lines.
Note 7: The input common-mode voltage or either input signal voltage should not be allowed to go negative by more than 0.3V. The upper end of the common-
mode voltage range is V
magnitude of V
Note 8: Positive excursions of input voltage may exceed the power supply level. As long as the other voltage remains within the common-mode range, the
comparator will provide a proper output state. The low input voltage state must not be less than −0.3 V
supply, if used) (at 25°C).
Note 9: Parameter guaranteed by V
Note 10: The value for V
Note 11: Pre and post irradiation limits are identical to those listed under AC and DC electrical characteristics except as listed in the “Post Radiation Limits” table.
These parts may be dose rate sensitive in a space environment and demonstrate enhanced low dose rate effect. Radiation end point limits for the noted parameters
are guaranteed only for the conditions as specified in Mil-Std-883, Method 1019, Condition A.
Note 12: SMD 5962–8773901 only
Note 13: Human Body model, 1.5 KΩ in series with 100 pF
Note 14: The maximum power dissipation must be derated at elevated temperatures and is dictated by T
junction to ambient thermal resistance), and T
θ
Note 15: Low dose rate testing has been performed on a wafer-by-wafer basis, per test method 1019, condition D, MIL-STD-883, with no enhanced low dose
rate sensitivity (ELDRS) effect. Pre and post irradiation limits are identical to those listed under AC and DC electrical characteristics, except as listed in the “Post
Radiation Limits” table. Radiation end point limits for the noted parameters are guaranteed for only the conditions as specified in MIL-STD-883, Method 1019,
condition D.
JA
or the number given in the Absolute Maximum Ratings, whichever is lower.
+
.
+
Diff
−1.5V for Subgroup 1, or V
is not data logged during Read and Record.
IO
DC
tests
(at 25°)C.
+
can cause excessive heating and eventual destruction. When considering short circuits to ground, the maximum output
A
(ambient temperature). The maximum allowable power dissipation at any temperature is P
+
−2.0V for Subgroup 2 & 3. Either or both inputs can go to +30 V
+
.
9
+
voltage level (or to ground for a large overdrive) for the
DC
(or 0.3 V
Jmax
(maximum junction temperature), θ
DC
D
below the magnitude of the negative power
≤
DC
100mW), provided the output transistors
without damage, independent of the
Dmax
= (T
www.national.com
JA
Jmax
(Package
— T
A
) /