WM8523GEFL/RV Wolfson Microelectronics, WM8523GEFL/RV Datasheet - Page 24

• Manufacturer Part Number: WM8523GEFL/RV
• Description: IC, DAC, STEREO, 2VRMS, 2CH, 24QFN
• Manufacturer: Wolfson Microelectronics

Specifications of WM8523GEFL/RV

• Resolution (bits): 24bit
• Sampling Rate: 192kSPS
• Input Channel Type: Serial
• Digital Ic Case Style: QFN
• No. Of Pins: 24
• Operating Temperature Range: -40°C To +85°C
• Svhc: No SVHC (15-Dec-2010)
• Package: RoHS Compliant
• Data Interface: I2C, Serial, SPI
• Supply Voltage Range - Analogue: 2.97V To 3.63V
• Rohs Compliant: Yes

WM8523
DIGITAL AUDIO INTERFACE CONTROL
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Figure 22 DSP Mode Audio Interface (mode B, AIF_LRCLK_INV=1, Slave)
The control of the audio interface in software mode is achieved by register write. Dynamically changing
the audio data format may cause erroneous operation and is not recommended.
Digital audio data is transferred to the WM8523 via the digital audio interface. The DAC operates in
master or slave mode.
The DAC audio interface requires left/right frame clock (LRCLK) and bit clock (BCLK). These can be
supplied externally (slave mode) or they can be generated internally (master mode). Selection of master
and slave mode is achieved by setting AIF_MSTR bit in Register 3.
The frequency of LRCLK in master mode is dependent upon the DAC master clock frequency and the
AIF_SR[2:0] bits. The frequency of BCLK in master mode can be selected by AIF_BCLKDIV[2:0]. In
slave mode, the MCLK to LRCLK ratio can be auto-detected or set manually using the AIF_SR[2:0] bits.
Table 9 DAC Clocking Mode Control
AIF_CTRL1
AIF_CTRL2
REGISTER
ADDRESS
03h
04h
R3
R4
BIT
2:0
5:3
7
AIF_SR[2:0
AIF_MSTR
AIF_BCLK
DIV[2:0]
LABEL
DEFAULT
000
000
0
Master/Slave Select
0 = Slave
1 = Master
MCLK:LRCLK Ratio
000 = Auto detect
001 = 128fs
010 = 192fs
011 = 256fs
100 = 384fs
101 = 512fs
110 = 768fs
111 = 1152fs
BCLK Divider Control (Master Mode)
000 = MCLK/4
001 = MCLK/8
010 = 32fs
011 = 64fs
100 = 128fs
101 - 111 reserved
DESCRIPTION
PP, Rev 3.0, July 2009
Pre-Production
24