5M80ZT100C5N Altera, 5M80ZT100C5N Datasheet - Page 70

• Manufacturer Part Number: 5M80ZT100C5N
• Description: ALTERA
• Manufacturer: Altera
• Series: MAX Vr

Specifications of 5M80ZT100C5N

• Cpld Type: FLASH
• No. Of Macrocells: 64
• No. Of I/o's: 79
• Propagation Delay: 7.5ns
• Global Clock Setup Time: 4.6ns
• Frequency: 118.3MHz
• Supply Voltage Range: 1.71V To 1.89V
• Programmable Type: In System Programmable
• Delay Time Tpd(1) Max: 7.5ns
• Voltage Supply - Internal: 1.71 V ~ 1.89 V
• Number Of Logic Elements/blocks: 80
• Number Of Macrocells: 64
• Number Of Gates: -
• Number Of I /o: 79
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP
• Rohs Compliant: Yes
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Training
Online training
68
Course Category
Embedded systems
Device-specific
training
Scripting
Altera Product Catalog
Altera Free Online Training Courses (Courses Are Approximately One Hour in Length)
Course Titles
Designing with the Nios II Processor and SOPC Builder (Day 1)
(note: this training is equivalent to day 1 of the instructor-led course of the same name)
Developing Software for the Nios II Processor: Tools Overview
Developing Software for the Nios II Processor: Design Flow
Using SOPC Builder
Using the Nios II Processor
Nios II Processor and SOPC Builder
Custom Components for SOPC Builder
Developing Software for the Nios II Processor: Nios II Software Build Tools for Eclipse
Nios II Software Build Tools for Eclipse and BSP Editor (Quartus II Software 10.0 Update)
Developing Software for the Nios II Processor: Debug Primer
Developing Software for the Nios II Processor: HAL Primer
Developing Software for the Nios II Processor: Software Build Flow - (Part 1)
Developing Software for the Nios II Processor: Software Build Flow - (Part 2)
Developing Software for the Nios II Processor: C2H Fundamentals
Nios II Floating-Point Custom Instructions
Developing Software for the Nios II Processor: MMU and MPU
Avalon Verification Suite
Lauterbach Debug Tools
Industrial Ethernet Solutions
Introduction to Graphics
Introduction to D/AVE GPU
Power Distribution Network Design for Stratix III and Stratix IV FPGAs
Power Distribution Network Design Using Altera PDN Design Tools
Configuring Altera FPGAs
The Quartus II Software Design Flow for HardCopy ASICs
MAX IIZ CPLDs in Mobile Handsets
Command-Line Scripting
Introduction to Tcl Part 1 of 2
Introduction to Tcl Part 2 of 2
Basic Quartus II Software Tcl Scripting Part 1 of 2
Basic Quartus II Software Tcl Scripting Part 2 of 2
•
2011
•
www.altera.com
Languages
English only
English and Chinese
English and Chinese
English and Chinese
English, Chinese,
and Japanese
Japanese only
English only
English and Japanese
English only
English and Chinese
English, Chinese,
and Japanese
English only
English only
English and Japanese
English and Chinese
English and Chinese
English only
English only
English and Chinese
English only
English only
English and Chinese
English only
English and Chinese
English only
English and Chinese
English only
English only
English only
English only
English only