MRF89XAM9A-I/RM Microchip Technology, MRF89XAM9A-I/RM Datasheet - Page 61

• Manufacturer Part Number: MRF89XAM9A-I/RM
• Description: WiFi / 802.11 Modules & Development Tools 915MHz Sub-GHz Transceiver Mod
• Manufacturer: Microchip Technology

Specifications of MRF89XAM9A-I/RM

• Modulation Type: FSK, OOK
• Data Rate Max: 200Kbps
• Sensitivity: -113dBm
• Supply Voltage Range: 2.1V To 3.6V
• Module Interface: SPI, 4-Wire
• Supply Current: 25mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

3.2
3.2.1
The crystal oscillator (XTAL) forms the reference
oscillator of an Integer-N PLL. The crystal reference
frequency and the software controlled dividers R, P,
and S determine the output frequency of the PLL. The
guidelines for selecting the appropriate crystal with
specifications are explained in Section 4.6 “Crystal
Specification and Selection Guidelines”.
3.2.2
The buffered clock output is a signal derived from f
It can be used as a reference clock (or a sub-multiple
of it) for the host microcontroller and is an output on the
CLKOUT pin (pin 19). The pin is activated using the
CLKOCNTRL bit (CLKOUTREG<7>). The output
frequency (CLKOUT) division ratio is programmed
through
(CLKOFREQ5-CLK0FREQ1) in the Clock Output
Control Register (CLKOUTREG<6:2>). The two uses
of the CLKOUT output are:
• To provide a clock output for a host microcontroller,
• To
3.2.3
The registers associated with the Clock and its control
are:
• GCONREG (Register 2-1)
• CLKOUTREG (Register 2-28).
3.2.4
The frequency synthesizer of the MRF89XA is a fully
integrated integer-N type PLL. The PLL circuit requires
only five external components for the PLL loop filter
and the VCO tank circuit.
© 2010 Microchip Technology Inc.
Note:
thus saving the cost of an additional oscillator.
CLKOUT can be made available in any operation
mode, except Sleep mode, and is automatically
enabled at power-up.
Measurement of the CLKOUT signal enables
simple software trimming of the initial crystal
tolerance.
Note:
provide
Frequency Synthesis Description
the
REFERENCE OSCILLATOR
Use the recommended values provided in
the Bill Of Materials (BOM) in Section 4.7
“Bill of Materials” for any PLL prototype
design.
BUFFERED CLOCK OUTPUT
CLKOUT is disabled when the MRF89XA
is in Sleep mode. If Sleep mode is used,
the host microcontroller must have provi-
sions to run from its own clock source.
CLOCK REGISTERS
PHASE-LOCKED LOOP (PLL)
an
Clock
oscillator
Out
reference
Frequency
output.
Preliminary
bits
xtal
.
3.2.4.1
With
conditions must be met to ensure correct operation:
• The comparison frequency, F
• However the PLLBW must be sufficiently high to
• Because the divider ratio R determines F
The following criteria govern the R, P, and S values for
the PLL block:
• 64 ≤ R ≤ 169
• P+1 > S
• PLLBW = 15 kHz nominal
• Start-up times and reference frequency drives as
3.2.4.2
The MRF89XA features a PLL lock detect indicator.
This is useful for optimizing power consumption, by
adjusting the frequency synthesizer wake-up time
(TSFS). For more information on TSFS, refer
Table 5-4. The lock status is available by reading the
Lock Status of PLL bit (LSTSPLL) in the FIFO
Transmit
Configuration register (FTPRIREG<1>), and must be
cleared by writing a ‘1’ to this same register. The
lock status can also be seen on the PLOCK pin (pin
23) of the device, by setting the LENPLL bit
(FTPRIREG<0>).
3.2.5
The registers associated with the PLL are:
• GCONREG (Register 2-1)
• FTPRIREG (Register 2-15).
3.2.6
To guarantee the optimum operation of the VCO over
the MRF89XA’s frequency and temperature ranges,
the settings listed in Table 3-1 should be programmed
into the MRF89XA.
Frequency Detector (PFD) input must remain
higher than six times the PLL bandwidth (PLLBW)
to guarantee loop stability and to reject harmonics
of the comparison frequency F
expressed in the inequality:
allow adequate PLL lock times.
should be set close to 119, leading to F
100 kHz, which will ensure suitable PLL stability
and speed.
specified
Note:
F
COMP
integer-N
PLL
The LENPLL bit latches high each time the
PLL locks and must be reset by writing a
‘1’ to LENPLL.
PLL REGISTERS
SW SETTINGS OF THE VCO
≥ 6 * PLLBW
PLL Requirements
PLL Lock Detection Indicator
PLL
and
architecture,
RSSI
MRF89XA
COMP
Interrupt
DS70622B-page 61
COMP
, of the Phase
the
. This is
COMP
COMP
following
Request
, it
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