MRF89XAM9A-I/RM Microchip Technology, MRF89XAM9A-I/RM Datasheet - Page 42

• Manufacturer Part Number: MRF89XAM9A-I/RM
• Description: WiFi / 802.11 Modules & Development Tools 915MHz Sub-GHz Transceiver Mod
• Manufacturer: Microchip Technology

Specifications of MRF89XAM9A-I/RM

• Modulation Type: FSK, OOK
• Data Rate Max: 200Kbps
• Sensitivity: -113dBm
• Supply Voltage Range: 2.1V To 3.6V
• Module Interface: SPI, 4-Wire
• Supply Current: 25mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

2.15.2
REGISTER 2-15:
DS70622B-page 42
MRF89XA
bit 7
R = Readable bit
-n = Value at POR
r = Reserved
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
Note 1: Setting this bit to ‘0’ disables the RSSI IRQ source. It can be left enabled at any time, and the user can
FIFOFM
R/W-0
FIFO TRANSMIT PLL AND RSSI
INTERRUPT REQUEST
CONFIGURATION REGISTER
DETAILS
choose to map this interrupt to IRQ0/IRQ1 or not.
FIFOFM: FIFO Filling Method bits
This bit decides the method of filling FIFO (supports Buffer mode only)
1 = Manually controlled by FIFO fill
0 = Automatically starts when a sync word is detected (default)
FIFOFSC: FIFO Filling Status or Control bits
This bit indicate the status of FIFO filling and also controls the filling up of FIFO
(supports Buffer Mode only)
STATUS: Reading (FIFOFM = 0)
1 = FIFO getting filled (
0 = FIFO filling completed / stopped
CONTROL: Writing (FIFOFM = 1), clears the bit and waits for a new sync word (FOVRCLR = 0)
1 = Start filling the FIFO
0 = Stop filling the FIFO
TXDONE: Transmit Done bit
This bit selects and IRQ source.
1 = TXDONE (goes high when the last bit has left the shift register).
0 = TX still in process
IRQ0TXST: Transmit Start with IRQ0 bit
This bit indicates transmit start condition with IRQ0 as source.
If DMODE1:DMODE0 = 01
1 = Transmit starts if FIFO is not empty, IRQ0 mapped to FIFOEMPTY
0 = Transmit starts if FIFO is full, IRQ0 mapped to FIFOEMPTY (default)
If DMODE1:DMODE0 = 1x
1 = Transmit starts if FIFO is not empty, IRQ0 mapped to FIFOEMPTY
0 = Start transmission when the number of bytes in FIFO is greater than or equal to threshold set by
Reserved: Reserved bit
1 = Set bit to ‘1’ (required)
0 = Reserved (default)
RIRQS: RSSI IRQ Source
This bit indicates IRQ source as RSSI
1 = Detected signal is above the value determined by the RTIVAL<7:0> bits (RSTHIREG<7:0>)
0 = Detected signal is less than the value determined by the RTIVAL<7:0> bits (RSTHIREG<7:0>)
Writing a ‘1’ for this bit clears RIRQS.
FIFOFSC
R/W-0
the FTINT<5:0> bits (FIFOCREG<5:0), IRQ0 mapped to FIFO_THRESHOLD
FTPRIREG: FIFO TRANSMIT PLL AND RSSI INTERRUPT REQUEST
CONFIGURATION REGISTER (ADDRESS:0x0E) (POR:0x01)
W = Writable bit
‘1’ = Bit is set
TXDONE
R/W-0
sync word has been detected)
(1)
IRQ0TXST
Buffer Mode:
Packet Mode:
R/W-0
Preliminary
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
—
r
RIRQS
R/W-0
© 2010 Microchip Technology Inc.
x = Bit is unknown
LSTSPLL
R/W-0
LENPLL
R/W-1
bit 0