C8051F124TB Silicon Laboratories Inc, C8051F124TB Datasheet - Page 80

• Manufacturer Part Number: C8051F124TB
• Description: MCU, MPU & DSP Development Tools With C8051F124 MCU
• Manufacturer: Silicon Laboratories Inc

Specifications of C8051F124TB

• Processor To Be Evaluated: C8051F12x and C8051F13x
• Interface Type: USB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
80
Bits7–3: AD0SC4–0: ADC0 SAR Conversion Clock Period Bits.
Bits2–0: AMP0GN2–0: ADC0 Internal Amplifier Gain (PGA).
SFR Page:
SFR Address:
AD0SC4
R/W
Bit7
SAR Conversion clock is derived from system clock by the following equation, where
AD0SC refers to the 5-bit value held in AD0SC4-0, and CLK
SAR clock (Note: the ADC0 SAR Conversion Clock should be less than or equal to
2.5 MHz).
When the AD0SC bits are equal to 00000b, the SAR Conversion clock is equal to SYSCLK
to facilitate faster ADC conversions at slower SYSCLK speeds.
000: Gain = 1
001: Gain = 2
010: Gain = 4
011: Gain = 8
10x: Gain = 16
11x: Gain = 0.5
AD0SC
0
0xBC
AD0SC3
R/W
Bit6
SFR Definition 6.3. ADC0CF: ADC0 Configuration
=
------------------------------- - 1
2 C
AD0SC2
 LK
SYSCLK
R/W
Bit5
SAR0
AD0SC1
R/W
Bit4
–
Rev. 1.4
AD0SC0 AMP0GN2 AMP0GN1 AMP0GN0 11111000
R/W
Bit3

R/W
AD0SC 00000b
Bit2
SAR0

R/W
Bit1
refers to the desired ADC0

R/W
Bit0
Reset Value