STEVAL-ISV009V1 STMicroelectronics, STEVAL-ISV009V1 Datasheet - Page 25

• Manufacturer Part Number: STEVAL-ISV009V1
• Description: Power Management Modules & Development Tools DUAL STG DC/AC CNVRT DEMO BRD
• Manufacturer: STMicroelectronics
• Series: -r

Specifications of STEVAL-ISV009V1

• Design Resources: STEVAL-ISV009V1 BOM STEVAL-ISV009V1 Schematic
• Main Purpose: DC/DC, Step Up
• Outputs And Type: 1, Non-Isolated
• Power - Output: -
• Voltage - Output: 36V
• Current - Output: -
• Voltage - Input: -
• Regulator Topology: Boost
• Frequency - Switching: -
• Board Type: Fully Populated
• Utilized Ic / Part: SPV1020
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AN3392
Figure 22. Frame structure: register read operation
The SPV1020 register file is accessible by the host through the SPI bus. Thus, the host can
read some register of SPV1020 control parameters. Each data frame includes at least one
command byte followed by some data bytes whose direction depends on the type of
command. If the command byte requires some data to be read from the register file, those
data are transmitted from the slave to the master through the MISO pin; thus the master
appends a number of NOPs (0x00) to the command, so that the entire data can be
transmitted,
If the SS wire goes high before the completion of a command byte in the data frame, the
SPV1020 rejects that byte and the frame is closed; then the next data frame is considered
as a new one, starting with a command byte.
Some data words can be longer than 8 bits, such as ADC results (10 bits); in such cases,
data is first extended to the nearest multiple of one byte (it is right justified), then it is split
into bytes, e.g. the ADC result R is formatted as follows:
Table 1.
Byte 1
Byte 2
Figure
Data format for words longer than 8 bits
MSB
Bit 7
R7
0
22. In other words, the master has to transmit a byte to receive a byte.
Bit 6
R6
0
Doc ID XXXXX Rev 1
Bit 5
R5
0
Bit 4
R4
0
Bit 3
R3
0
Bit 2
R2
0
Voltage regulation
Bit 1
MSB
R9
R1
Bit 0
LSB
LSB
R8
R0
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